[AArch64] Update test cases for Exynos M3
Update any test case relevant for Exynos M3.
llvm-svn: 323775
diff --git a/llvm/test/CodeGen/AArch64/arm64-ldp-cluster.ll b/llvm/test/CodeGen/AArch64/arm64-ldp-cluster.ll
index 75b02b9..80b6777 100644
--- a/llvm/test/CodeGen/AArch64/arm64-ldp-cluster.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-ldp-cluster.ll
@@ -1,6 +1,7 @@
; REQUIRES: asserts
; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a57 -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
-; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=exynos-m1 -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck --check-prefix=EXYNOS %s
+; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=exynos-m1 -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck --check-prefix=EXYNOSM1 %s
+; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=exynos-m3 -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
; Test ldr clustering.
; CHECK: ********** MI Scheduling **********
@@ -8,11 +9,11 @@
; CHECK: Cluster ld/st SU(1) - SU(2)
; CHECK: SU(1): %{{[0-9]+}}:gpr32 = LDRWui
; CHECK: SU(2): %{{[0-9]+}}:gpr32 = LDRWui
-; EXYNOS: ********** MI Scheduling **********
-; EXYNOS-LABEL: ldr_int:%bb.0
-; EXYNOS: Cluster ld/st SU(1) - SU(2)
-; EXYNOS: SU(1): %{{[0-9]+}}:gpr32 = LDRWui
-; EXYNOS: SU(2): %{{[0-9]+}}:gpr32 = LDRWui
+; EXYNOSM1: ********** MI Scheduling **********
+; EXYNOSM1-LABEL: ldr_int:%bb.0
+; EXYNOSM1: Cluster ld/st SU(1) - SU(2)
+; EXYNOSM1: SU(1): %{{[0-9]+}}:gpr32 = LDRWui
+; EXYNOSM1: SU(2): %{{[0-9]+}}:gpr32 = LDRWui
define i32 @ldr_int(i32* %a) nounwind {
%p1 = getelementptr inbounds i32, i32* %a, i32 1
%tmp1 = load i32, i32* %p1, align 2
@@ -28,11 +29,11 @@
; CHECK: Cluster ld/st SU(1) - SU(2)
; CHECK: SU(1): %{{[0-9]+}}:gpr64 = LDRSWui
; CHECK: SU(2): %{{[0-9]+}}:gpr64 = LDRSWui
-; EXYNOS: ********** MI Scheduling **********
-; EXYNOS-LABEL: ldp_sext_int:%bb.0
-; EXYNOS: Cluster ld/st SU(1) - SU(2)
-; EXYNOS: SU(1): %{{[0-9]+}}:gpr64 = LDRSWui
-; EXYNOS: SU(2): %{{[0-9]+}}:gpr64 = LDRSWui
+; EXYNOSM1: ********** MI Scheduling **********
+; EXYNOSM1-LABEL: ldp_sext_int:%bb.0
+; EXYNOSM1: Cluster ld/st SU(1) - SU(2)
+; EXYNOSM1: SU(1): %{{[0-9]+}}:gpr64 = LDRSWui
+; EXYNOSM1: SU(2): %{{[0-9]+}}:gpr64 = LDRSWui
define i64 @ldp_sext_int(i32* %p) nounwind {
%tmp = load i32, i32* %p, align 4
%add.ptr = getelementptr inbounds i32, i32* %p, i64 1
@@ -49,11 +50,11 @@
; CHECK: Cluster ld/st SU(2) - SU(1)
; CHECK: SU(1): %{{[0-9]+}}:gpr32 = LDURWi
; CHECK: SU(2): %{{[0-9]+}}:gpr32 = LDURWi
-; EXYNOS: ********** MI Scheduling **********
-; EXYNOS-LABEL: ldur_int:%bb.0
-; EXYNOS: Cluster ld/st SU(2) - SU(1)
-; EXYNOS: SU(1): %{{[0-9]+}}:gpr32 = LDURWi
-; EXYNOS: SU(2): %{{[0-9]+}}:gpr32 = LDURWi
+; EXYNOSM1: ********** MI Scheduling **********
+; EXYNOSM1-LABEL: ldur_int:%bb.0
+; EXYNOSM1: Cluster ld/st SU(2) - SU(1)
+; EXYNOSM1: SU(1): %{{[0-9]+}}:gpr32 = LDURWi
+; EXYNOSM1: SU(2): %{{[0-9]+}}:gpr32 = LDURWi
define i32 @ldur_int(i32* %a) nounwind {
%p1 = getelementptr inbounds i32, i32* %a, i32 -1
%tmp1 = load i32, i32* %p1, align 2
@@ -69,11 +70,11 @@
; CHECK: Cluster ld/st SU(3) - SU(4)
; CHECK: SU(3): %{{[0-9]+}}:gpr64 = LDRSWui
; CHECK: SU(4): undef %{{[0-9]+}}.sub_32:gpr64 = LDRWui
-; EXYNOS: ********** MI Scheduling **********
-; EXYNOS-LABEL: ldp_half_sext_zext_int:%bb.0
-; EXYNOS: Cluster ld/st SU(3) - SU(4)
-; EXYNOS: SU(3): %{{[0-9]+}}:gpr64 = LDRSWui
-; EXYNOS: SU(4): undef %{{[0-9]+}}.sub_32:gpr64 = LDRWui
+; EXYNOSM1: ********** MI Scheduling **********
+; EXYNOSM1-LABEL: ldp_half_sext_zext_int:%bb.0
+; EXYNOSM1: Cluster ld/st SU(3) - SU(4)
+; EXYNOSM1: SU(3): %{{[0-9]+}}:gpr64 = LDRSWui
+; EXYNOSM1: SU(4): undef %{{[0-9]+}}.sub_32:gpr64 = LDRWui
define i64 @ldp_half_sext_zext_int(i64* %q, i32* %p) nounwind {
%tmp0 = load i64, i64* %q, align 4
%tmp = load i32, i32* %p, align 4
@@ -92,11 +93,11 @@
; CHECK: Cluster ld/st SU(3) - SU(4)
; CHECK: SU(3): undef %{{[0-9]+}}.sub_32:gpr64 = LDRWui
; CHECK: SU(4): %{{[0-9]+}}:gpr64 = LDRSWui
-; EXYNOS: ********** MI Scheduling **********
-; EXYNOS-LABEL: ldp_half_zext_sext_int:%bb.0
-; EXYNOS: Cluster ld/st SU(3) - SU(4)
-; EXYNOS: SU(3): undef %{{[0-9]+}}.sub_32:gpr64 = LDRWui
-; EXYNOS: SU(4): %{{[0-9]+}}:gpr64 = LDRSWui
+; EXYNOSM1: ********** MI Scheduling **********
+; EXYNOSM1-LABEL: ldp_half_zext_sext_int:%bb.0
+; EXYNOSM1: Cluster ld/st SU(3) - SU(4)
+; EXYNOSM1: SU(3): undef %{{[0-9]+}}.sub_32:gpr64 = LDRWui
+; EXYNOSM1: SU(4): %{{[0-9]+}}:gpr64 = LDRSWui
define i64 @ldp_half_zext_sext_int(i64* %q, i32* %p) nounwind {
%tmp0 = load i64, i64* %q, align 4
%tmp = load i32, i32* %p, align 4
@@ -115,11 +116,11 @@
; CHECK-NOT: Cluster ld/st
; CHECK: SU(1): %{{[0-9]+}}:gpr32 = LDRWui
; CHECK: SU(2): %{{[0-9]+}}:gpr32 = LDRWui
-; EXYNOS: ********** MI Scheduling **********
-; EXYNOS-LABEL: ldr_int_volatile:%bb.0
-; EXYNOS-NOT: Cluster ld/st
-; EXYNOS: SU(1): %{{[0-9]+}}:gpr32 = LDRWui
-; EXYNOS: SU(2): %{{[0-9]+}}:gpr32 = LDRWui
+; EXYNOSM1: ********** MI Scheduling **********
+; EXYNOSM1-LABEL: ldr_int_volatile:%bb.0
+; EXYNOSM1-NOT: Cluster ld/st
+; EXYNOSM1: SU(1): %{{[0-9]+}}:gpr32 = LDRWui
+; EXYNOSM1: SU(2): %{{[0-9]+}}:gpr32 = LDRWui
define i32 @ldr_int_volatile(i32* %a) nounwind {
%p1 = getelementptr inbounds i32, i32* %a, i32 1
%tmp1 = load volatile i32, i32* %p1, align 2
@@ -135,9 +136,9 @@
; CHECK: Cluster ld/st SU(1) - SU(3)
; CHECK: SU(1): %{{[0-9]+}}:fpr128 = LDRQui
; CHECK: SU(3): %{{[0-9]+}}:fpr128 = LDRQui
-; EXYNOS: ********** MI Scheduling **********
-; EXYNOS-LABEL: ldq_cluster:%bb.0
-; EXYNOS-NOT: Cluster ld/st
+; EXYNOSM1: ********** MI Scheduling **********
+; EXYNOSM1-LABEL: ldq_cluster:%bb.0
+; EXYNOSM1-NOT: Cluster ld/st
define <2 x i64> @ldq_cluster(i64* %p) {
%a1 = bitcast i64* %p to <2 x i64>*
%tmp1 = load <2 x i64>, < 2 x i64>* %a1, align 8