[Docs] Add tablegen backend for target opcode documentation
This is a tablegen backend to generate documentation for the opcodes that exist
for each target. For each opcode, it lists the assembly string, the names and
types of all operands, and the flags and predicates that apply to the opcode.
Differential revision: https://reviews.llvm.org/D31025
llvm-svn: 318155
diff --git a/llvm/utils/TableGen/TableGen.cpp b/llvm/utils/TableGen/TableGen.cpp
index 7353c53..debc771 100644
--- a/llvm/utils/TableGen/TableGen.cpp
+++ b/llvm/utils/TableGen/TableGen.cpp
@@ -28,6 +28,7 @@
GenEmitter,
GenRegisterInfo,
GenInstrInfo,
+ GenInstrDocs,
GenAsmWriter,
GenAsmMatcher,
GenDisassembler,
@@ -62,6 +63,8 @@
"Generate registers and register classes info"),
clEnumValN(GenInstrInfo, "gen-instr-info",
"Generate instruction descriptions"),
+ clEnumValN(GenInstrDocs, "gen-instr-docs",
+ "Generate instruction documentation"),
clEnumValN(GenCallingConv, "gen-callingconv",
"Generate calling convention descriptions"),
clEnumValN(GenAsmWriter, "gen-asm-writer",
@@ -124,6 +127,9 @@
case GenInstrInfo:
EmitInstrInfo(Records, OS);
break;
+ case GenInstrDocs:
+ EmitInstrDocs(Records, OS);
+ break;
case GenCallingConv:
EmitCallingConv(Records, OS);
break;