[GlobalISel][IRTranslator] Teach the pass how to translate Add instructions.
llvm-svn: 260549
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index 704b019..e10338d 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -12,8 +12,13 @@
#include "llvm/CodeGen/GlobalISel/IRTranslator.h"
+#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/IR/Constant.h"
#include "llvm/IR/Function.h"
+#include "llvm/IR/Type.h"
+#include "llvm/IR/Value.h"
#define DEBUG_TYPE "irtranslator"
@@ -21,15 +26,49 @@
char IRTranslator::ID = 0;
+const VRegsSequence &IRTranslator::getOrCreateVRegs(const Value *Val) {
+ VRegsSequence &ValRegSequence = ValToVRegs[Val];
+ // Check if this is the first time we see Val.
+ if (ValRegSequence.empty()) {
+ // Fill ValRegsSequence with the sequence of registers
+ // we need to concat together to produce the value.
+ assert(Val->getType()->isSized() &&
+ "Don't know how to create an empty vreg");
+ assert(!Val->getType()->isAggregateType() && "Not yet implemented");
+ unsigned Size = Val->getType()->getPrimitiveSizeInBits();
+ unsigned VReg = MRI->createGenericVirtualRegister(Size);
+ ValRegSequence.push_back(VReg);
+ assert(isa<Constant>(Val) && "Not yet implemented");
+ }
+ assert(ValRegSequence.size() == 1 &&
+ "We support only one vreg per value at the moment");
+ return ValRegSequence;
+}
+
+MachineBasicBlock &IRTranslator::getOrCreateBB(const BasicBlock *BB) {
+ MachineBasicBlock *&MBB = BBToMBB[BB];
+ if (!MBB) {
+ MachineFunction &MF = MIRBuilder->getMF();
+ MBB = MF.CreateMachineBasicBlock();
+ MF.push_back(MBB);
+ }
+ return *MBB;
+}
+
bool IRTranslator::translateADD(const Instruction &Inst) {
// Get or create a virtual register for each value.
// Unless the value is a Constant => loadimm cst?
// or inline constant each time?
// Creation of a virtual register needs to have a size.
- return false;
+ unsigned Op0 = *getOrCreateVRegs(Inst.getOperand(0)).begin();
+ unsigned Op1 = *getOrCreateVRegs(Inst.getOperand(1)).begin();
+ unsigned Res = *getOrCreateVRegs(&Inst).begin();
+ MIRBuilder->buildInstr(TargetOpcode::G_ADD, Res, Op0, Op1);
+ return true;
}
bool IRTranslator::translate(const Instruction &Inst) {
+ MIRBuilder->setDebugLoc(Inst.getDebugLoc());
switch(Inst.getOpcode()) {
case Instruction::Add: {
return translateADD(Inst);
@@ -53,7 +92,11 @@
bool IRTranslator::runOnMachineFunction(MachineFunction &MF) {
const Function &F = *MF.getFunction();
+ MIRBuilder->setFunction(MF);
+ MRI = &MF.getRegInfo();
for (const BasicBlock &BB: F) {
+ MachineBasicBlock &MBB = getOrCreateBB(&BB);
+ MIRBuilder->setBasicBlock(MBB);
for (const Instruction &Inst: BB) {
bool Succeeded = translate(Inst);
if (!Succeeded) {