TableGen: Check scheduling models for completeness
TableGen checks at compiletime that for scheduling models with
"CompleteModel = 1" one of the following holds:
- Is marked with the hasNoSchedulingInfo flag
- The instruction is a subclass of Sched
- There are InstRW definitions in the scheduling model
Typical steps necessary to complete a model:
- Ensure all pseudo instructions that are expanded before machine
scheduling (usually everything handled with EmitYYY() functions in
XXXTargetLowering).
- If a CPU does not support some instructions mark the corresponding
resource unsupported: "WriteRes<WriteXXX, []> { let Unsupported = 1; }".
- Add missing scheduling information.
Differential Revision: http://reviews.llvm.org/D17747
llvm-svn: 262384
diff --git a/llvm/lib/Target/AArch64/AArch64SchedA53.td b/llvm/lib/Target/AArch64/AArch64SchedA53.td
index d709bee..ad5505b 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedA53.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedA53.td
@@ -26,6 +26,7 @@
let MispredictPenalty = 9; // Based on "Cortex-A53 Software Optimisation
// Specification - Instruction Timings"
// v 1.0 Spreadsheet
+ let CompleteModel = 0;
}
diff --git a/llvm/lib/Target/AArch64/AArch64SchedA57.td b/llvm/lib/Target/AArch64/AArch64SchedA57.td
index ca4457a..4b3a9b0 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedA57.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedA57.td
@@ -30,6 +30,7 @@
// Enable partial & runtime unrolling. The magic number is chosen based on
// experiments and benchmarking data.
let LoopMicroOpBufferSize = 16;
+ let CompleteModel = 0;
}
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AArch64/AArch64SchedCyclone.td b/llvm/lib/Target/AArch64/AArch64SchedCyclone.td
index 419169c..21e2bc2 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedCyclone.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedCyclone.td
@@ -17,6 +17,7 @@
let MicroOpBufferSize = 192; // Based on the reorder buffer.
let LoadLatency = 4; // Optimistic load latency.
let MispredictPenalty = 16; // 14-19 cycles are typical.
+ let CompleteModel = 0;
}
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AArch64/AArch64SchedKryo.td b/llvm/lib/Target/AArch64/AArch64SchedKryo.td
index 347104a..dc01199 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedKryo.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedKryo.td
@@ -26,6 +26,7 @@
// Enable partial & runtime unrolling. The magic number is chosen based on
// experiments and benchmarking data.
let LoopMicroOpBufferSize = 16;
+ let CompleteModel = 0;
}
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AMDGPU/SISchedule.td b/llvm/lib/Target/AMDGPU/SISchedule.td
index cd77e51..40b37c4 100644
--- a/llvm/lib/Target/AMDGPU/SISchedule.td
+++ b/llvm/lib/Target/AMDGPU/SISchedule.td
@@ -39,8 +39,12 @@
// instructions and have VALU rates, but write to the SALU (i.e. VOPC
// instructions)
-def SIFullSpeedModel : SchedMachineModel;
-def SIQuarterSpeedModel : SchedMachineModel;
+def SIFullSpeedModel : SchedMachineModel {
+ let CompleteModel = 0;
+}
+def SIQuarterSpeedModel : SchedMachineModel {
+ let CompleteModel = 0;
+}
// BufferSize = 0 means the processors are in-order.
let BufferSize = 0 in {
diff --git a/llvm/lib/Target/ARM/ARMScheduleA8.td b/llvm/lib/Target/ARM/ARMScheduleA8.td
index 2c63825..154a889 100644
--- a/llvm/lib/Target/ARM/ARMScheduleA8.td
+++ b/llvm/lib/Target/ARM/ARMScheduleA8.td
@@ -1070,6 +1070,7 @@
// This is overriden by OperandCycles if the
// Itineraries are queried instead.
let MispredictPenalty = 13; // Based on estimate of pipeline depth.
+ let CompleteModel = 0;
let Itineraries = CortexA8Itineraries;
}
diff --git a/llvm/lib/Target/Hexagon/HexagonScheduleV4.td b/llvm/lib/Target/Hexagon/HexagonScheduleV4.td
index 67af147..0f462c9 100644
--- a/llvm/lib/Target/Hexagon/HexagonScheduleV4.td
+++ b/llvm/lib/Target/Hexagon/HexagonScheduleV4.td
@@ -199,6 +199,7 @@
let IssueWidth = 4;
let Itineraries = HexagonItinerariesV4;
let LoadLatency = 1;
+ let CompleteModel = 0;
}
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/Hexagon/HexagonScheduleV55.td b/llvm/lib/Target/Hexagon/HexagonScheduleV55.td
index d9ad25d..2bc4a3d 100644
--- a/llvm/lib/Target/Hexagon/HexagonScheduleV55.td
+++ b/llvm/lib/Target/Hexagon/HexagonScheduleV55.td
@@ -163,6 +163,7 @@
let IssueWidth = 4;
let Itineraries = HexagonItinerariesV55;
let LoadLatency = 1;
+ let CompleteModel = 0;
}
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/Hexagon/HexagonScheduleV60.td b/llvm/lib/Target/Hexagon/HexagonScheduleV60.td
index 2ccff82..a92377f 100644
--- a/llvm/lib/Target/Hexagon/HexagonScheduleV60.td
+++ b/llvm/lib/Target/Hexagon/HexagonScheduleV60.td
@@ -303,6 +303,7 @@
let IssueWidth = 4;
let Itineraries = HexagonItinerariesV60;
let LoadLatency = 1;
+ let CompleteModel = 0;
}
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/Mips/MipsScheduleP5600.td b/llvm/lib/Target/Mips/MipsScheduleP5600.td
index d32ae4f..cee4287 100644
--- a/llvm/lib/Target/Mips/MipsScheduleP5600.td
+++ b/llvm/lib/Target/Mips/MipsScheduleP5600.td
@@ -13,7 +13,7 @@
int LoadLatency = 4;
int MispredictPenalty = 8; // TODO: Estimated
- let CompleteModel = 1;
+ let CompleteModel = 0;
}
let SchedModel = MipsP5600Model in {
diff --git a/llvm/lib/Target/PowerPC/PPCSchedule440.td b/llvm/lib/Target/PowerPC/PPCSchedule440.td
index 04a43bc..e4a2c3b 100644
--- a/llvm/lib/Target/PowerPC/PPCSchedule440.td
+++ b/llvm/lib/Target/PowerPC/PPCSchedule440.td
@@ -602,6 +602,8 @@
// This is overriden by OperandCycles if the
// Itineraries are queried instead.
+ let CompleteModel = 0;
+
let Itineraries = PPC440Itineraries;
}
diff --git a/llvm/lib/Target/PowerPC/PPCScheduleA2.td b/llvm/lib/Target/PowerPC/PPCScheduleA2.td
index 21a357a..9cdfd0b 100644
--- a/llvm/lib/Target/PowerPC/PPCScheduleA2.td
+++ b/llvm/lib/Target/PowerPC/PPCScheduleA2.td
@@ -166,6 +166,8 @@
// Itineraries are queried instead.
let MispredictPenalty = 13;
+ let CompleteModel = 0;
+
let Itineraries = PPCA2Itineraries;
}
diff --git a/llvm/lib/Target/PowerPC/PPCScheduleE500mc.td b/llvm/lib/Target/PowerPC/PPCScheduleE500mc.td
index 36b8517..262c715 100644
--- a/llvm/lib/Target/PowerPC/PPCScheduleE500mc.td
+++ b/llvm/lib/Target/PowerPC/PPCScheduleE500mc.td
@@ -316,5 +316,7 @@
// This is overriden by OperandCycles if the
// Itineraries are queried instead.
+ let CompleteModel = 0;
+
let Itineraries = PPCE500mcItineraries;
}
diff --git a/llvm/lib/Target/PowerPC/PPCScheduleE5500.td b/llvm/lib/Target/PowerPC/PPCScheduleE5500.td
index 7c2693e..642a5ae 100644
--- a/llvm/lib/Target/PowerPC/PPCScheduleE5500.td
+++ b/llvm/lib/Target/PowerPC/PPCScheduleE5500.td
@@ -376,5 +376,7 @@
// This is overriden by OperandCycles if the
// Itineraries are queried instead.
+ let CompleteModel = 0;
+
let Itineraries = PPCE5500Itineraries;
}
diff --git a/llvm/lib/Target/PowerPC/PPCScheduleG5.td b/llvm/lib/Target/PowerPC/PPCScheduleG5.td
index a3b73ab..a001b59 100644
--- a/llvm/lib/Target/PowerPC/PPCScheduleG5.td
+++ b/llvm/lib/Target/PowerPC/PPCScheduleG5.td
@@ -124,6 +124,8 @@
// Itineraries are queried instead.
let MispredictPenalty = 16;
+ let CompleteModel = 0;
+
let Itineraries = G5Itineraries;
}
diff --git a/llvm/lib/Target/PowerPC/PPCScheduleP7.td b/llvm/lib/Target/PowerPC/PPCScheduleP7.td
index 267f567..26c80c9 100644
--- a/llvm/lib/Target/PowerPC/PPCScheduleP7.td
+++ b/llvm/lib/Target/PowerPC/PPCScheduleP7.td
@@ -391,6 +391,8 @@
// Try to make sure we have at least 10 dispatch groups in a loop.
let LoopMicroOpBufferSize = 40;
+ let CompleteModel = 0;
+
let Itineraries = P7Itineraries;
}
diff --git a/llvm/lib/Target/PowerPC/PPCScheduleP8.td b/llvm/lib/Target/PowerPC/PPCScheduleP8.td
index 69e6d05..b7083e6 100644
--- a/llvm/lib/Target/PowerPC/PPCScheduleP8.td
+++ b/llvm/lib/Target/PowerPC/PPCScheduleP8.td
@@ -400,6 +400,8 @@
// Try to make sure we have at least 10 dispatch groups in a loop.
let LoopMicroOpBufferSize = 60;
+ let CompleteModel = 0;
+
let Itineraries = P8Itineraries;
}
diff --git a/llvm/lib/Target/X86/X86Schedule.td b/llvm/lib/Target/X86/X86Schedule.td
index a261356..46c88c4 100644
--- a/llvm/lib/Target/X86/X86Schedule.td
+++ b/llvm/lib/Target/X86/X86Schedule.td
@@ -640,6 +640,7 @@
let LoadLatency = 4;
let HighLatency = 10;
let PostRAScheduler = 0;
+ let CompleteModel = 0;
}
include "X86ScheduleAtom.td"
diff --git a/llvm/lib/Target/X86/X86ScheduleAtom.td b/llvm/lib/Target/X86/X86ScheduleAtom.td
index 4c559c9..a5b4401 100644
--- a/llvm/lib/Target/X86/X86ScheduleAtom.td
+++ b/llvm/lib/Target/X86/X86ScheduleAtom.td
@@ -544,6 +544,7 @@
// simple loops, expand by a small factor to hide the backedge cost.
let LoopMicroOpBufferSize = 10;
let PostRAScheduler = 1;
+ let CompleteModel = 0;
let Itineraries = AtomItineraries;
}