diff --git a/llvm/lib/Target/AMDGPU/SISchedule.td b/llvm/lib/Target/AMDGPU/SISchedule.td
index cd77e51..40b37c4 100644
--- a/llvm/lib/Target/AMDGPU/SISchedule.td
+++ b/llvm/lib/Target/AMDGPU/SISchedule.td
@@ -39,8 +39,12 @@
 // instructions and have VALU rates, but write to the SALU (i.e. VOPC
 // instructions)
 
-def SIFullSpeedModel : SchedMachineModel;
-def SIQuarterSpeedModel : SchedMachineModel;
+def SIFullSpeedModel : SchedMachineModel {
+  let CompleteModel = 0;
+}
+def SIQuarterSpeedModel : SchedMachineModel {
+  let CompleteModel = 0;
+}
 
 // BufferSize = 0 means the processors are in-order.
 let BufferSize = 0 in {