commit 18b2c2f13c6541495746ffc43cb5fa56b8bb8c91
author Chris Lattner <sabre@nondot.org> Sat May 14 12:03:10 2005 +0000
committer Chris Lattner <sabre@nondot.org> Sat May 14 12:03:10 2005 +0000
tree 31d1665f4da6be464d9eb3ff34e0d95ba1a895a8
parent 1b3520c90b4102132ae8349a4c15eca12e354665

Pass i64 values correctly split in reg/mem to fastcc calls.

This fixes fourinarow with -enable-x86-fastcc.

llvm-svn: 22022

llvm/lib/Target/X86/X86ISelPattern.cpp

diff --git a/llvm/lib/Target/X86/X86ISelPattern.cpp b/llvm/lib/Target/X86/X86ISelPattern.cpp
index 66bbe6f..4c77ff6 100644
--- a/llvm/lib/Target/X86/X86ISelPattern.cpp
+++ b/llvm/lib/Target/X86/X86ISelPattern.cpp
@@ -750,8 +750,7 @@
           SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
           PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
           Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
-                                       Args[i].first, PtrOff,
-                                       DAG.getSrcValue(NULL)));
+                                       Hi, PtrOff, DAG.getSrcValue(NULL)));
           ArgOffset += 4;
         }
         break;