Replace Triple with a new TargetTuple in MCTargetDesc/* and related. NFC.
Summary:
This is the first patch in the series to migrate Triple's (which are ambiguous)
to TargetTuple's (which aren't).
For the moment, TargetTuple simply passes all requests to the Triple object it
holds. Once it has replaced Triple, it will start to implement the interface in
a more suitable way.
This change makes some changes to the public C++ API. In particular,
InitMCSubtargetInfo(), createMCRelocationInfo(), and createMCSymbolizer()
now take TargetTuples instead of Triples. The other public C++ API's have
been left as-is for the moment to reduce patch size.
This commit also contains a trivial patch to clang to account for the C++ API
change.
Reviewers: rengolin
Subscribers: jyknight, dschuff, arsenm, rampitec, danalbert, srhines, javed.absar, dsanders, echristo, emaste, jholewinski, tberghammer, ted, jfb, llvm-commits, rengolin
Differential Revision: http://reviews.llvm.org/D10969
llvm-svn: 247683
diff --git a/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp b/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
index cd482b3..31c43b0 100644
--- a/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
@@ -72,7 +72,7 @@
HexagonSubtarget::HexagonSubtarget(const Triple &TT, StringRef CPU,
StringRef FS, const TargetMachine &TM)
- : HexagonGenSubtargetInfo(TT, CPU, FS), CPUString(CPU),
+ : HexagonGenSubtargetInfo(TargetTuple(TT), CPU, FS), CPUString(CPU),
InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this),
FrameLowering() {
diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
index 99ea2fa..105e78f 100644
--- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
+++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
@@ -309,7 +309,7 @@
namespace llvm {
MCAsmBackend *createHexagonAsmBackend(Target const &T,
MCRegisterInfo const & /*MRI*/,
- const Triple &TT, StringRef CPU) {
+ const TargetTuple &TT, StringRef CPU) {
uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
return new HexagonAsmBackend(T, OSABI, CPU);
}
diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp
index 51d2f1c..113b622 100644
--- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp
+++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp
@@ -18,7 +18,7 @@
// Pin the vtable to this file.
void HexagonMCAsmInfo::anchor() {}
-HexagonMCAsmInfo::HexagonMCAsmInfo(const Triple &TT) {
+HexagonMCAsmInfo::HexagonMCAsmInfo(const TargetTuple &TT) {
Data16bitsDirective = "\t.half\t";
Data32bitsDirective = "\t.word\t";
Data64bitsDirective = nullptr; // .xword is only supported by V9.
diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.h b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.h
index a8456b4..de9702e 100644
--- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.h
+++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.h
@@ -18,13 +18,13 @@
#include "llvm/MC/MCAsmInfoELF.h"
namespace llvm {
-class Triple;
+class TargetTuple;
class HexagonMCAsmInfo : public MCAsmInfoELF {
void anchor() override;
public:
- explicit HexagonMCAsmInfo(const Triple &TT);
+ explicit HexagonMCAsmInfo(const TargetTuple &TT);
};
} // namespace llvm
diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
index 53305d8..ca42634 100644
--- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
+++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
@@ -46,14 +46,15 @@
return X;
}
-static MCRegisterInfo *createHexagonMCRegisterInfo(const Triple &TT) {
+static MCRegisterInfo *createHexagonMCRegisterInfo(const TargetTuple &TT) {
MCRegisterInfo *X = new MCRegisterInfo();
InitHexagonMCRegisterInfo(X, Hexagon::R0);
return X;
}
-static MCSubtargetInfo *
-createHexagonMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
+static MCSubtargetInfo *createHexagonMCSubtargetInfo(const TargetTuple &TT,
+ StringRef CPU,
+ StringRef FS) {
return createHexagonMCSubtargetInfoImpl(TT, CPU, FS);
}
@@ -138,7 +139,7 @@
}
static MCAsmInfo *createHexagonMCAsmInfo(const MCRegisterInfo &MRI,
- const Triple &TT) {
+ const TargetTuple &TT) {
MCAsmInfo *MAI = new HexagonMCAsmInfo(TT);
// VirtualFP = (R30 + #0).
@@ -149,7 +150,7 @@
return MAI;
}
-static MCCodeGenInfo *createHexagonMCCodeGenInfo(const Triple &TT,
+static MCCodeGenInfo *createHexagonMCCodeGenInfo(const TargetTuple &TT,
Reloc::Model RM,
CodeModel::Model CM,
CodeGenOpt::Level OL) {
@@ -160,7 +161,7 @@
return X;
}
-static MCInstPrinter *createHexagonMCInstPrinter(const Triple &T,
+static MCInstPrinter *createHexagonMCInstPrinter(const TargetTuple &TT,
unsigned SyntaxVariant,
const MCAsmInfo &MAI,
const MCInstrInfo &MII,
@@ -178,7 +179,7 @@
return new HexagonTargetAsmStreamer(S, OS, IsVerboseAsm, *InstPrint);
}
-static MCStreamer *createMCStreamer(Triple const &T, MCContext &Context,
+static MCStreamer *createMCStreamer(const TargetTuple &TT, MCContext &Context,
MCAsmBackend &MAB, raw_pwrite_stream &OS,
MCCodeEmitter *Emitter, bool RelaxAll) {
return createHexagonELFStreamer(Context, MAB, OS, Emitter);
diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h
index cb62650..a5c23bd 100644
--- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h
+++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h
@@ -27,7 +27,7 @@
class MCRegisterInfo;
class MCSubtargetInfo;
class Target;
-class Triple;
+class TargetTuple;
class StringRef;
class raw_ostream;
class raw_pwrite_stream;
@@ -44,7 +44,7 @@
MCAsmBackend *createHexagonAsmBackend(Target const &T,
MCRegisterInfo const &MRI,
- const Triple &TT, StringRef CPU);
+ const TargetTuple &TT, StringRef CPU);
MCObjectWriter *createHexagonELFObjectWriter(raw_pwrite_stream &OS,
uint8_t OSABI, StringRef CPU);