ARM64: use 32-bit moves for constants where possible.
If we know that a particular 64-bit constant has all high bits zero, then we
can rely on the fact that 32-bit ARM64 instructions automatically zero out the
high bits of an x-register. This gives the expansion logic less constraints to
satisfy and so sometimes allows it to pick better sequences.
Came up while porting test/CodeGen/AArch64/movw-consts.ll: this will allow a
32-bit MOVN to be used in @test8 soon.
llvm-svn: 206379
diff --git a/llvm/test/CodeGen/ARM64/aapcs.ll b/llvm/test/CodeGen/ARM64/aapcs.ll
index fc1266c..e4889b7 100644
--- a/llvm/test/CodeGen/ARM64/aapcs.ll
+++ b/llvm/test/CodeGen/ARM64/aapcs.ll
@@ -80,7 +80,7 @@
define void @test_variadic() {
call void(i32, ...)* @variadic(i32 0, i64 1, double 2.0)
; CHECK: fmov d0, #2.0
-; CHECK: orr x1, xzr, #0x1
+; CHECK: orr w1, wzr, #0x1
; CHECK: bl variadic
ret void
}
diff --git a/llvm/test/CodeGen/ARM64/atomic.ll b/llvm/test/CodeGen/ARM64/atomic.ll
index 4a957b8..13502f4 100644
--- a/llvm/test/CodeGen/ARM64/atomic.ll
+++ b/llvm/test/CodeGen/ARM64/atomic.ll
@@ -17,14 +17,14 @@
define i64 @val_compare_and_swap_64(i64* %p) {
; CHECK-LABEL: val_compare_and_swap_64:
-; CHECK: orr [[NEWVAL_REG:x[0-9]+]], xzr, #0x4
-; CHECK: orr [[OLDVAL_REG:x[0-9]+]], xzr, #0x7
+; CHECK: orr w[[NEWVAL_REG:[0-9]+]], wzr, #0x4
+; CHECK: orr w[[OLDVAL_REG:[0-9]+]], wzr, #0x7
; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
; CHECK: ldxr [[RESULT:x[0-9]+]], [x0]
-; CHECK: cmp [[RESULT]], [[OLDVAL_REG]]
+; CHECK: cmp [[RESULT]], x[[OLDVAL_REG]]
; CHECK: b.ne [[LABEL2:.?LBB[0-9]+_[0-9]+]]
-; CHECK-NOT: stxr [[NEWVAL_REG]], [[NEWVAL_REG]]
-; CHECK: stxr [[SCRATCH_REG:w[0-9]+]], [[NEWVAL_REG]], [x0]
+; CHECK-NOT: stxr x[[NEWVAL_REG]], x[[NEWVAL_REG]]
+; CHECK: stxr [[SCRATCH_REG:w[0-9]+]], x[[NEWVAL_REG]], [x0]
; CHECK: cbnz [[SCRATCH_REG]], [[LABEL]]
; CHECK: [[LABEL2]]:
%val = cmpxchg i64* %p, i64 7, i64 4 monotonic monotonic
@@ -47,10 +47,10 @@
define i64 @fetch_and_nand_64(i64* %p) {
; CHECK-LABEL: fetch_and_nand_64:
-; CHECK: orr [[OLDVAL_REG:x[0-9]+]], xzr, #0x7
+; CHECK: orr w[[OLDVAL_REG:[0-9]+]], wzr, #0x7
; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
; CHECK: ldaxr [[DEST_REG:x[0-9]+]], [x0]
-; CHECK: bic [[SCRATCH2_REG:x[0-9]+]], [[OLDVAL_REG]], [[DEST_REG]]
+; CHECK: bic [[SCRATCH2_REG:x[0-9]+]], x[[OLDVAL_REG]], [[DEST_REG]]
; CHECK: stlxr [[SCRATCH_REG:w[0-9]+]], [[SCRATCH2_REG]], [x0]
; CHECK: cbnz [[SCRATCH_REG]], [[LABEL]]
; CHECK: mov x0, [[DEST_REG]]
@@ -74,10 +74,10 @@
define i64 @fetch_and_or_64(i64* %p) {
; CHECK: fetch_and_or_64:
-; CHECK: orr [[OLDVAL_REG:x[0-9]+]], xzr, #0x7
+; CHECK: orr w[[OLDVAL_REG:[0-9]+]], wzr, #0x7
; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
; CHECK: ldxr [[DEST_REG:x[0-9]+]], [x0]
-; CHECK: orr [[SCRATCH2_REG:x[0-9]+]], [[DEST_REG]], [[OLDVAL_REG]]
+; CHECK: orr [[SCRATCH2_REG:x[0-9]+]], [[DEST_REG]], x[[OLDVAL_REG]]
; CHECK: stxr [[SCRATCH_REG:w[0-9]+]], [[SCRATCH2_REG]], [x0]
; CHECK: cbnz [[SCRATCH_REG]], [[LABEL]]
; CHECK: mov x0, [[DEST_REG]]
diff --git a/llvm/test/CodeGen/ARM64/bitfield-extract.ll b/llvm/test/CodeGen/ARM64/bitfield-extract.ll
index 96b6967..40dee71 100644
--- a/llvm/test/CodeGen/ARM64/bitfield-extract.ll
+++ b/llvm/test/CodeGen/ARM64/bitfield-extract.ll
@@ -376,10 +376,10 @@
; CHECK-LABEL: fct17:
; CHECK: ldr [[REG1:x[0-9]+]],
; Create the constant
-; CHECK: movz [[REGCST:x[0-9]+]], #26, lsl #16
-; CHECK: movk [[REGCST]], #33120
+; CHECK: movz w[[REGCST:[0-9]+]], #26, lsl #16
+; CHECK: movk w[[REGCST]], #33120
; Do the masking
-; CHECK: and [[REG2:x[0-9]+]], [[REG1]], [[REGCST]]
+; CHECK: and [[REG2:x[0-9]+]], [[REG1]], x[[REGCST]]
; CHECK-NEXT: bfm [[REG2]], x1, #16, #18
; lsr is an alias of ubfm
; CHECK-NEXT: ubfm [[REG3:x[0-9]+]], [[REG2]], #2, #61
diff --git a/llvm/test/CodeGen/ARM64/const-addr.ll b/llvm/test/CodeGen/ARM64/const-addr.ll
index c77a6db..977628a 100644
--- a/llvm/test/CodeGen/ARM64/const-addr.ll
+++ b/llvm/test/CodeGen/ARM64/const-addr.ll
@@ -5,8 +5,8 @@
; Test if the constant base address gets only materialized once.
define i32 @test1() nounwind {
; CHECK-LABEL: test1
-; CHECK: movz x8, #1039, lsl #16
-; CHECK-NEXT: movk x8, #49152
+; CHECK: movz w8, #1039, lsl #16
+; CHECK-NEXT: movk w8, #49152
; CHECK-NEXT: ldp w9, w10, [x8, #4]
; CHECK: ldr w8, [x8, #12]
%at = inttoptr i64 68141056 to %T*
diff --git a/llvm/test/CodeGen/ARM64/csel.ll b/llvm/test/CodeGen/ARM64/csel.ll
index cbf1769..d0ee61c 100644
--- a/llvm/test/CodeGen/ARM64/csel.ll
+++ b/llvm/test/CodeGen/ARM64/csel.ll
@@ -126,7 +126,7 @@
entry:
; CHECK-LABEL: foo10:
; CHECK: cmp x0, #0
-; CHECK: orr x[[REG:[0-9]+]], xzr, #0x4
+; CHECK: orr w[[REG:[0-9]+]], wzr, #0x4
; CHECK: csinv x0, x[[REG]], x[[REG]], ne
%tobool = icmp ne i64 %v, 0
%cond = select i1 %tobool, i64 4, i64 -5
@@ -148,7 +148,7 @@
entry:
; CHECK-LABEL: foo12:
; CHECK: cmp x0, #0
-; CHECK: orr x[[REG:[0-9]+]], xzr, #0x4
+; CHECK: orr w[[REG:[0-9]+]], wzr, #0x4
; CHECK: csneg x0, x[[REG]], x[[REG]], ne
%tobool = icmp ne i64 %v, 0
%cond = select i1 %tobool, i64 4, i64 -4
@@ -203,7 +203,7 @@
entry:
; CHECK-LABEL: foo17:
; CHECK: cmp x0, x1
-; CHECK: orr x[[REG:[0-9]+]], xzr, #0x1
+; CHECK: orr w[[REG:[0-9]+]], wzr, #0x1
; CHECK: csinc x0, x[[REG]], x[[REG]], le
%cmp = icmp sgt i64 %a, %b
%. = select i1 %cmp, i64 2, i64 1
@@ -214,7 +214,7 @@
entry:
; CHECK-LABEL: foo18:
; CHECK: cmp x0, x1
-; CHECK: orr x[[REG:[0-9]+]], xzr, #0x1
+; CHECK: orr w[[REG:[0-9]+]], wzr, #0x1
; CHECK: csinc x0, x[[REG]], x[[REG]], gt
%cmp = icmp sgt i64 %a, %b
%. = select i1 %cmp, i64 1, i64 2
diff --git a/llvm/test/CodeGen/ARM64/long-shift.ll b/llvm/test/CodeGen/ARM64/long-shift.ll
index 6f37044..caa486a 100644
--- a/llvm/test/CodeGen/ARM64/long-shift.ll
+++ b/llvm/test/CodeGen/ARM64/long-shift.ll
@@ -3,8 +3,8 @@
define i128 @shl(i128 %r, i128 %s) nounwind readnone {
; CHECK-LABEL: shl:
; CHECK: lslv [[XREG_0:x[0-9]+]], x1, x2
-; CHECK-NEXT: orr [[XREG_1:x[0-9]+]], xzr, #0x40
-; CHECK-NEXT: sub [[XREG_2:x[0-9]+]], [[XREG_1]], x2
+; CHECK-NEXT: orr w[[XREG_1:[0-9]+]], wzr, #0x40
+; CHECK-NEXT: sub [[XREG_2:x[0-9]+]], x[[XREG_1]], x2
; CHECK-NEXT: lsrv [[XREG_3:x[0-9]+]], x0, [[XREG_2]]
; CHECK-NEXT: orr [[XREG_6:x[0-9]+]], [[XREG_3]], [[XREG_0]]
; CHECK-NEXT: sub [[XREG_4:x[0-9]+]], x2, #64
@@ -20,10 +20,10 @@
}
define i128 @ashr(i128 %r, i128 %s) nounwind readnone {
-; CHECK: ashr:
+; CHECK-LABEL: ashr:
; CHECK: lsrv [[XREG_0:x[0-9]+]], x0, x2
-; CHECK-NEXT: orr [[XREG_1:x[0-9]+]], xzr, #0x40
-; CHECK-NEXT: sub [[XREG_2:x[0-9]+]], [[XREG_1]], x2
+; CHECK-NEXT: orr w[[XREG_1:[0-9]+]], wzr, #0x40
+; CHECK-NEXT: sub [[XREG_2:x[0-9]+]], x[[XREG_1]], x2
; CHECK-NEXT: lslv [[XREG_3:x[0-9]+]], x1, [[XREG_2]]
; CHECK-NEXT: orr [[XREG_4:x[0-9]+]], [[XREG_0]], [[XREG_3]]
; CHECK-NEXT: sub [[XREG_5:x[0-9]+]], x2, #64
@@ -40,10 +40,10 @@
}
define i128 @lshr(i128 %r, i128 %s) nounwind readnone {
-; CHECK: lshr:
+; CHECK-LABEL: lshr:
; CHECK: lsrv [[XREG_0:x[0-9]+]], x0, x2
-; CHECK-NEXT: orr [[XREG_1:x[0-9]+]], xzr, #0x40
-; CHECK-NEXT: sub [[XREG_2:x[0-9]+]], [[XREG_1]], x2
+; CHECK-NEXT: orr w[[XREG_1:[0-9]+]], wzr, #0x40
+; CHECK-NEXT: sub [[XREG_2:x[0-9]+]], x[[XREG_1]], x2
; CHECK-NEXT: lslv [[XREG_3:x[0-9]+]], x1, [[XREG_2]]
; CHECK-NEXT: orr [[XREG_4:x[0-9]+]], [[XREG_0]], [[XREG_3]]
; CHECK-NEXT: sub [[XREG_5:x[0-9]+]], x2, #64
diff --git a/llvm/test/CodeGen/ARM64/patchpoint.ll b/llvm/test/CodeGen/ARM64/patchpoint.ll
index 9e5ed6f..dd555b0 100644
--- a/llvm/test/CodeGen/ARM64/patchpoint.ll
+++ b/llvm/test/CodeGen/ARM64/patchpoint.ll
@@ -67,11 +67,11 @@
entry:
; CHECK-LABEL: jscall_patchpoint_codegen2:
; CHECK: Ltmp
-; CHECK: orr x{{.+}}, xzr, #0x6
+; CHECK: orr w{{.+}}, wzr, #0x6
; CHECK-NEXT: str x{{.+}}, [sp, #24]
; CHECK-NEXT: orr w{{.+}}, wzr, #0x4
; CHECK-NEXT: str w{{.+}}, [sp, #16]
-; CHECK-NEXT: orr x{{.+}}, xzr, #0x2
+; CHECK-NEXT: orr w{{.+}}, wzr, #0x2
; CHECK-NEXT: str x{{.+}}, [sp]
; CHECK: Ltmp
; CHECK-NEXT: movz x16, #65535, lsl #32
@@ -88,15 +88,15 @@
entry:
; CHECK-LABEL: jscall_patchpoint_codegen3:
; CHECK: Ltmp
-; CHECK: movz x{{.+}}, #10
+; CHECK: movz w{{.+}}, #10
; CHECK-NEXT: str x{{.+}}, [sp, #48]
; CHECK-NEXT: orr w{{.+}}, wzr, #0x8
; CHECK-NEXT: str w{{.+}}, [sp, #36]
-; CHECK-NEXT: orr x{{.+}}, xzr, #0x6
+; CHECK-NEXT: orr w{{.+}}, wzr, #0x6
; CHECK-NEXT: str x{{.+}}, [sp, #24]
; CHECK-NEXT: orr w{{.+}}, wzr, #0x4
; CHECK-NEXT: str w{{.+}}, [sp, #16]
-; CHECK-NEXT: orr x{{.+}}, xzr, #0x2
+; CHECK-NEXT: orr w{{.+}}, wzr, #0x2
; CHECK-NEXT: str x{{.+}}, [sp]
; CHECK: Ltmp
; CHECK-NEXT: movz x16, #65535, lsl #32