[RISCV][NFC] Update RISCVInstrInfoC.td to match usual instruction naming convention
When an instruction mnemonic contains a '.', we usually name the instruction
with a _ in that place. e.g. fadd.s -> FADD_S.
This patch updates RISCVInstrInfoC.td to do the same, e.g. c.nop -> C_NOP.
Also includes some minor formatting changes in RISCVInstrInfoC.td to better
align it with the formatting conventions in the rest of the backend.
llvm-svn: 320560
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index 932bc71..563edc9 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -186,14 +186,16 @@
// Add implied SP operand for instructions *SP compressed instructions. The SP
// operand isn't explicitly encoded in the instruction.
static void addImplySP(MCInst &Inst, int64_t Address, const void *Decoder) {
- if (Inst.getOpcode() == RISCV::CLWSP || Inst.getOpcode() == RISCV::CSWSP ||
- Inst.getOpcode() == RISCV::CLDSP || Inst.getOpcode() == RISCV::CSDSP ||
- Inst.getOpcode() == RISCV::CFLWSP || Inst.getOpcode() == RISCV::CFSWSP ||
- Inst.getOpcode() == RISCV::CFLDSP || Inst.getOpcode() == RISCV::CFSDSP ||
- Inst.getOpcode() == RISCV::CADDI4SPN) {
+ if (Inst.getOpcode() == RISCV::C_LWSP || Inst.getOpcode() == RISCV::C_SWSP ||
+ Inst.getOpcode() == RISCV::C_LDSP || Inst.getOpcode() == RISCV::C_SDSP ||
+ Inst.getOpcode() == RISCV::C_FLWSP ||
+ Inst.getOpcode() == RISCV::C_FSWSP ||
+ Inst.getOpcode() == RISCV::C_FLDSP ||
+ Inst.getOpcode() == RISCV::C_FSDSP ||
+ Inst.getOpcode() == RISCV::C_ADDI4SPN) {
DecodeGPRRegisterClass(Inst, 2, Address, Decoder);
}
- if (Inst.getOpcode() == RISCV::CADDI16SP) {
+ if (Inst.getOpcode() == RISCV::C_ADDI16SP) {
DecodeGPRRegisterClass(Inst, 2, Address, Decoder);
DecodeGPRRegisterClass(Inst, 2, Address, Decoder);
}