commit 1a02d30c87307b9330946a1feab91b14c3fa5e57
author Matt Arsenault <Matthew.Arsenault@amd.com> Fri May 17 12:59:27 2019 +0000
committer Matt Arsenault <Matthew.Arsenault@amd.com> Fri May 17 12:59:27 2019 +0000
tree 316bee34998a273a1f996559642a37024427613f
parent f3dccc64af5d7fc10d30d37c5eaa535373287964

AMDGPU: Fix unused variable warnings in release builds

llvm-svn: 361030

llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index 4b45b70..6ee40cb 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -882,20 +882,18 @@
   MachineIRBuilder &B) const {
   B.setInstr(MI);
 
+  const LLT S1 = LLT::scalar(1);
+  const LLT S64 = LLT::scalar(64);
+
   unsigned Src = MI.getOperand(1).getReg();
-  LLT Ty = MRI.getType(Src);
-  assert(Ty.isScalar() && Ty.getSizeInBits() == 64);
+  assert(MRI.getType(Src) == S64);
 
   // result = trunc(src)
   // if (src > 0.0 && src != result)
   //   result += 1.0
 
-  LLT S1 = LLT::scalar(1);
-  LLT S64 = LLT::scalar(64);
-
   auto Trunc = B.buildInstr(TargetOpcode::G_INTRINSIC_TRUNC, {S64}, {Src});
 
-
   const auto Zero = B.buildFConstant(S64, 0.0);
   const auto One = B.buildFConstant(S64, 1.0);
   auto Lt0 = B.buildFCmp(CmpInst::FCMP_OGT, S1, Src, Zero);
@@ -929,13 +927,12 @@
   MachineIRBuilder &B) const {
   B.setInstr(MI);
 
-  unsigned Src = MI.getOperand(1).getReg();
-  LLT Ty = MRI.getType(Src);
-  assert(Ty.isScalar() && Ty.getSizeInBits() == 64);
+  const LLT S1 = LLT::scalar(1);
+  const LLT S32 = LLT::scalar(32);
+  const LLT S64 = LLT::scalar(64);
 
-  LLT S1 = LLT::scalar(1);
-  LLT S32 = LLT::scalar(32);
-  LLT S64 = LLT::scalar(64);
+  unsigned Src = MI.getOperand(1).getReg();
+  assert(MRI.getType(Src) == S64);
 
   // TODO: Should this use extract since the low half is unused?
   auto Unmerge = B.buildUnmerge({S32, S32}, Src);