commit 1aaad6970cee96c214cc663bc7ae2cecb6fd1e7c
author Tom Stellard <thomas.stellard@amd.com> Mon Jul 21 16:55:33 2014 +0000
committer Tom Stellard <thomas.stellard@amd.com> Mon Jul 21 16:55:33 2014 +0000
tree fa24d65509767cb9ac91843d7c3d5c4e4644bc37
parent ced7b43a064c696a98fd6f2a0a8e972a07e4cdeb

R600/SI: Add instruction shrinking pass

This pass converts 64-bit instructions to 32-bit when possible.

llvm-svn: 213561

llvm/test/CodeGen/R600/setuo.ll

diff --git a/llvm/test/CodeGen/R600/setuo.ll b/llvm/test/CodeGen/R600/setuo.ll
index 3b1db8b..33007fc 100644
--- a/llvm/test/CodeGen/R600/setuo.ll
+++ b/llvm/test/CodeGen/R600/setuo.ll
@@ -1,7 +1,7 @@
 ;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s
 
 ;CHECK-LABEL: @main
-;CHECK: V_CMP_U_F32_e64 s[0:1], {{[sv][0-9]+, [sv][0-9]+}}, 0, 0
+;CHECK: V_CMP_U_F32_e32 vcc, {{[sv][0-9]+, v[0-9]+}}
 
 define void @main(float %p) {
 main_body: