[DAGCombine] Fix for PR37563
While searching for loads to be narrowed, equal sized loads were not
added to the list, resulting in anyext loads not being converted to
zext loads.
https://bugs.llvm.org/show_bug.cgi?id=35763
Differential Revision: https://reviews.llvm.org/D41628
llvm-svn: 321862
diff --git a/llvm/test/CodeGen/ARM/and-load-combine.ll b/llvm/test/CodeGen/ARM/and-load-combine.ll
index 2b92778..69b00ed 100644
--- a/llvm/test/CodeGen/ARM/and-load-combine.ll
+++ b/llvm/test/CodeGen/ARM/and-load-combine.ll
@@ -852,8 +852,7 @@
; ARM: @ %bb.0: @ %entry
; ARM-NEXT: ldrb r0, [r0]
; ARM-NEXT: uxtb r2, r2
-; ARM-NEXT: and r0, r0, r1
-; ARM-NEXT: uxtb r1, r0
+; ARM-NEXT: and r1, r0, r1
; ARM-NEXT: mov r0, #0
; ARM-NEXT: cmp r1, r2
; ARM-NEXT: movweq r0, #1
@@ -863,8 +862,7 @@
; ARMEB: @ %bb.0: @ %entry
; ARMEB-NEXT: ldrb r0, [r0]
; ARMEB-NEXT: uxtb r2, r2
-; ARMEB-NEXT: and r0, r0, r1
-; ARMEB-NEXT: uxtb r1, r0
+; ARMEB-NEXT: and r1, r0, r1
; ARMEB-NEXT: mov r0, #0
; ARMEB-NEXT: cmp r1, r2
; ARMEB-NEXT: movweq r0, #1
@@ -872,9 +870,8 @@
;
; THUMB1-LABEL: test6:
; THUMB1: @ %bb.0: @ %entry
-; THUMB1-NEXT: ldrb r0, [r0]
-; THUMB1-NEXT: ands r0, r1
-; THUMB1-NEXT: uxtb r3, r0
+; THUMB1-NEXT: ldrb r3, [r0]
+; THUMB1-NEXT: ands r3, r1
; THUMB1-NEXT: uxtb r2, r2
; THUMB1-NEXT: movs r0, #1
; THUMB1-NEXT: movs r1, #0
@@ -889,8 +886,7 @@
; THUMB2: @ %bb.0: @ %entry
; THUMB2-NEXT: ldrb r0, [r0]
; THUMB2-NEXT: uxtb r2, r2
-; THUMB2-NEXT: ands r0, r1
-; THUMB2-NEXT: uxtb r1, r0
+; THUMB2-NEXT: ands r1, r0
; THUMB2-NEXT: movs r0, #0
; THUMB2-NEXT: cmp r1, r2
; THUMB2-NEXT: it eq
diff --git a/llvm/test/CodeGen/X86/pr37563.ll b/llvm/test/CodeGen/X86/pr37563.ll
index f909eca..934902d 100644
--- a/llvm/test/CodeGen/X86/pr37563.ll
+++ b/llvm/test/CodeGen/X86/pr37563.ll
@@ -10,9 +10,10 @@
define void @PR35763() {
; CHECK-LABEL: PR35763:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: movzwl z+{{.*}}(%rip), %eax
-; CHECK-NEXT: orl {{.*}}(%rip), %eax
-; CHECK-NEXT: movq %rax, {{.*}}(%rip)
+; CHECK-NEXT: movzwl {{.*}}(%rip), %eax
+; CHECK-NEXT: movzwl z+{{.*}}(%rip), %ecx
+; CHECK-NEXT: orl %eax, %ecx
+; CHECK-NEXT: movq %rcx, {{.*}}(%rip)
; CHECK-NEXT: movl z+{{.*}}(%rip), %eax
; CHECK-NEXT: movzbl z+{{.*}}(%rip), %ecx
; CHECK-NEXT: shlq $32, %rcx