commit 1b0bc794e6be1714ece81c586f814a15f9f2f23a
author Jim Laskey <jlaskey@mac.com> Fri Dec 01 16:30:47 2006 +0000
committer Jim Laskey <jlaskey@mac.com> Fri Dec 01 16:30:47 2006 +0000
tree 15273fd5e017d9c8c02f804120815a51003a5df7
parent 311622f91273d1a2829d5d2df0321b48fa572ef7

1. In ppc64 mode we need only use one GPR.
2. Float values need to be promoted to double when they are vararg.

llvm-svn: 32074

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index d564ff7..d5129d5 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -1377,6 +1377,12 @@
       break;
     case MVT::f32:
     case MVT::f64:
+      if (isVarArg && isPPC64) {
+        // Float varargs need to be promoted to double.
+        if (Arg.getValueType() == MVT::f32)
+          Arg = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Arg);
+      }
+    
       if (FPR_idx != NumFPRs) {
         RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
 
@@ -1390,7 +1396,7 @@
             MemOpChains.push_back(Load.getValue(1));
             RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
           }
-          if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64) {
+          if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
             SDOperand ConstFour = DAG.getConstant(4, PtrOff.getValueType());
             PtrOff = DAG.getNode(ISD::ADD, PtrVT, PtrOff, ConstFour);
             SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0);