| commit | 1b1e25b7c51a4f021050cd693f77dc9d4a84740f | [log] [tgz] |
|---|---|---|
| author | Daniel Sanders <daniel.sanders@imgtec.com> | Fri Sep 27 10:08:31 2013 +0000 |
| committer | Daniel Sanders <daniel.sanders@imgtec.com> | Fri Sep 27 10:08:31 2013 +0000 |
| tree | 211f908076cebe1b5d93f3bd3dacd0fb618d9375 | |
| parent | db4c21f9945283f2e8d29c7a8a898512ebf37b52 [diff] |
[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode. llvm-svn: 191498