commit 1b1e25b7c51a4f021050cd693f77dc9d4a84740f
author Daniel Sanders <daniel.sanders@imgtec.com> Fri Sep 27 10:08:31 2013 +0000
committer Daniel Sanders <daniel.sanders@imgtec.com> Fri Sep 27 10:08:31 2013 +0000
tree 211f908076cebe1b5d93f3bd3dacd0fb618d9375
parent db4c21f9945283f2e8d29c7a8a898512ebf37b52

[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.

llvm-svn: 191498

llvm/test/CodeGen/Mips/msa/arithmetic.ll

diff --git a/llvm/test/CodeGen/Mips/msa/arithmetic.ll b/llvm/test/CodeGen/Mips/msa/arithmetic.ll
index 7dc758e..dc655e1 100644
--- a/llvm/test/CodeGen/Mips/msa/arithmetic.ll
+++ b/llvm/test/CodeGen/Mips/msa/arithmetic.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
+; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
 
 define void @add_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
   ; CHECK: add_v16i8: