commit 1b9fc8ed659589ee2f1d010adfd63f3d890c6ec3
author Matt Arsenault <Matthew.Arsenault@amd.com> Wed Sep 14 20:43:16 2016 +0000
committer Matt Arsenault <Matthew.Arsenault@amd.com> Wed Sep 14 20:43:16 2016 +0000
tree 27b082ad9831ad1d7dbddbd99b4c07e76e1db43e
parent 0ac172d8ede295c30946f6af2dafb68c7c7aa201

Finish renaming remaining analyzeBranch functions

llvm-svn: 281535

llvm/lib/Target/Sparc/SparcInstrInfo.cpp

diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.cpp b/llvm/lib/Target/Sparc/SparcInstrInfo.cpp
index 061b964..ea8ed83 100644
--- a/llvm/lib/Target/Sparc/SparcInstrInfo.cpp
+++ b/llvm/lib/Target/Sparc/SparcInstrInfo.cpp
@@ -271,7 +271,7 @@
   return 2;
 }
 
-unsigned SparcInstrInfo::RemoveBranch(MachineBasicBlock &MBB,
+unsigned SparcInstrInfo::removeBranch(MachineBasicBlock &MBB,
                                       int *BytesRemoved) const {
   assert(!BytesRemoved && "code size not handled");
 
@@ -295,7 +295,7 @@
   return Count;
 }
 
-bool SparcInstrInfo::ReverseBranchCondition(
+bool SparcInstrInfo::reverseBranchCondition(
     SmallVectorImpl<MachineOperand> &Cond) const {
   assert(Cond.size() == 1);
   SPCC::CondCodes CC = static_cast<SPCC::CondCodes>(Cond[0].getImm());