commit 1b9fc8ed659589ee2f1d010adfd63f3d890c6ec3
author Matt Arsenault <Matthew.Arsenault@amd.com> Wed Sep 14 20:43:16 2016 +0000
committer Matt Arsenault <Matthew.Arsenault@amd.com> Wed Sep 14 20:43:16 2016 +0000
tree 27b082ad9831ad1d7dbddbd99b4c07e76e1db43e
parent 0ac172d8ede295c30946f6af2dafb68c7c7aa201

Finish renaming remaining analyzeBranch functions

llvm-svn: 281535

llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp

diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
index c2b3811..bdc844d 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
@@ -363,7 +363,7 @@
   return false;
 }
 
-unsigned SystemZInstrInfo::RemoveBranch(MachineBasicBlock &MBB,
+unsigned SystemZInstrInfo::removeBranch(MachineBasicBlock &MBB,
                                         int *BytesRemoved) const {
   assert(!BytesRemoved && "code size not handled");
 
@@ -389,7 +389,7 @@
 }
 
 bool SystemZInstrInfo::
-ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
+reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
   assert(Cond.size() == 2 && "Invalid condition");
   Cond[1].setImm(Cond[1].getImm() ^ Cond[0].getImm());
   return false;