TableGen: Add operator !or
llvm-svn: 286936
diff --git a/llvm/docs/TableGen/LangRef.rst b/llvm/docs/TableGen/LangRef.rst
index 58da628..285572f 100644
--- a/llvm/docs/TableGen/LangRef.rst
+++ b/llvm/docs/TableGen/LangRef.rst
@@ -97,7 +97,9 @@
BangOperator: one of
:!eq !if !head !tail !con
:!add !shl !sra !srl !and
- :!cast !empty !subst !foreach !listconcat !strconcat
+ :!or !empty !subst !foreach !strconcat
+ :!cast !listconcat
+
Syntax
======
diff --git a/llvm/include/llvm/TableGen/Record.h b/llvm/include/llvm/TableGen/Record.h
index 393cafa..87ba6fd 100644
--- a/llvm/include/llvm/TableGen/Record.h
+++ b/llvm/include/llvm/TableGen/Record.h
@@ -798,7 +798,7 @@
///
class BinOpInit : public OpInit, public FoldingSetNode {
public:
- enum BinaryOp : uint8_t { ADD, AND, SHL, SRA, SRL, LISTCONCAT,
+ enum BinaryOp : uint8_t { ADD, AND, OR, SHL, SRA, SRL, LISTCONCAT,
STRCONCAT, CONCAT, EQ };
private:
diff --git a/llvm/lib/TableGen/Record.cpp b/llvm/lib/TableGen/Record.cpp
index 7f02c31..bffe271 100644
--- a/llvm/lib/TableGen/Record.cpp
+++ b/llvm/lib/TableGen/Record.cpp
@@ -865,6 +865,7 @@
}
case ADD:
case AND:
+ case OR:
case SHL:
case SRA:
case SRL: {
@@ -879,6 +880,7 @@
default: llvm_unreachable("Bad opcode!");
case ADD: Result = LHSv + RHSv; break;
case AND: Result = LHSv & RHSv; break;
+ case OR: Result = LHSv | RHSv; break;
case SHL: Result = LHSv << RHSv; break;
case SRA: Result = LHSv >> RHSv; break;
case SRL: Result = (uint64_t)LHSv >> (uint64_t)RHSv; break;
@@ -906,6 +908,7 @@
case CONCAT: Result = "!con"; break;
case ADD: Result = "!add"; break;
case AND: Result = "!and"; break;
+ case OR: Result = "!or"; break;
case SHL: Result = "!shl"; break;
case SRA: Result = "!sra"; break;
case SRL: Result = "!srl"; break;
diff --git a/llvm/lib/TableGen/TGLexer.cpp b/llvm/lib/TableGen/TGLexer.cpp
index c526fc0..5d6f7c2 100644
--- a/llvm/lib/TableGen/TGLexer.cpp
+++ b/llvm/lib/TableGen/TGLexer.cpp
@@ -472,6 +472,7 @@
.Case("con", tgtok::XConcat)
.Case("add", tgtok::XADD)
.Case("and", tgtok::XAND)
+ .Case("or", tgtok::XOR)
.Case("shl", tgtok::XSHL)
.Case("sra", tgtok::XSRA)
.Case("srl", tgtok::XSRL)
diff --git a/llvm/lib/TableGen/TGLexer.h b/llvm/lib/TableGen/TGLexer.h
index cbc30be..b5b5816 100644
--- a/llvm/lib/TableGen/TGLexer.h
+++ b/llvm/lib/TableGen/TGLexer.h
@@ -45,9 +45,9 @@
// Keywords.
Bit, Bits, Class, Code, Dag, Def, Foreach, Defm, Field, In, Int, Let, List,
MultiClass, String,
-
+
// !keywords.
- XConcat, XADD, XAND, XSRA, XSRL, XSHL, XListConcat, XStrConcat, XCast,
+ XConcat, XADD, XAND, XOR, XSRA, XSRL, XSHL, XListConcat, XStrConcat, XCast,
XSubst, XForEach, XHead, XTail, XEmpty, XIf, XEq,
// Integer value.
diff --git a/llvm/lib/TableGen/TGParser.cpp b/llvm/lib/TableGen/TGParser.cpp
index 0a6752b..ff5c96b 100644
--- a/llvm/lib/TableGen/TGParser.cpp
+++ b/llvm/lib/TableGen/TGParser.cpp
@@ -881,6 +881,7 @@
case tgtok::XConcat:
case tgtok::XADD:
case tgtok::XAND:
+ case tgtok::XOR:
case tgtok::XSRA:
case tgtok::XSRL:
case tgtok::XSHL:
@@ -899,6 +900,7 @@
case tgtok::XConcat: Code = BinOpInit::CONCAT;Type = DagRecTy::get(); break;
case tgtok::XADD: Code = BinOpInit::ADD; Type = IntRecTy::get(); break;
case tgtok::XAND: Code = BinOpInit::AND; Type = IntRecTy::get(); break;
+ case tgtok::XOR: Code = BinOpInit::OR; Type = IntRecTy::get(); break;
case tgtok::XSRA: Code = BinOpInit::SRA; Type = IntRecTy::get(); break;
case tgtok::XSRL: Code = BinOpInit::SRL; Type = IntRecTy::get(); break;
case tgtok::XSHL: Code = BinOpInit::SHL; Type = IntRecTy::get(); break;
@@ -1446,6 +1448,7 @@
case tgtok::XConcat:
case tgtok::XADD:
case tgtok::XAND:
+ case tgtok::XOR:
case tgtok::XSRA:
case tgtok::XSRL:
case tgtok::XSHL:
diff --git a/llvm/test/TableGen/math.td b/llvm/test/TableGen/math.td
index d966346..a8b9391 100644
--- a/llvm/test/TableGen/math.td
+++ b/llvm/test/TableGen/math.td
@@ -15,12 +15,18 @@
int Value = value;
}
+def v1022 : Int<1022>;
+
// CHECK: def v0
// CHECK: Value = 0
// CHECK: def v1
// CHECK: Value = 1
+// CHECK: def v1023
+// CHECK: Value = 1023
+def v1023 : Int<!or(v1022.Value, 1)>;
+
def v1024 : Int<1024>;
// CHECK: def v1024
// CHECK: Value = 1024
@@ -35,3 +41,7 @@
def v0 : Int<!and(v1024.Value, v2048.Value)>;
def v1 : Int<!and(v1025.Value, 1)>;
+
+// CHECK: def v3072
+// CHECK: Value = 3072
+def v3072 : Int<!or(v1024.Value, v2048.Value)>;