commit 1c8d933881a9990d2463c1e7772b4f4ebdb2198a
author Matt Arsenault <Matthew.Arsenault@amd.com> Tue Nov 15 06:49:28 2016 +0000
committer Matt Arsenault <Matthew.Arsenault@amd.com> Tue Nov 15 06:49:28 2016 +0000
tree 1aae04528751923c6c756e1a9b5e8e2ef8f7eaed
parent 76dbf26599388196d5f82a492c8d6004559983f7

TableGen: Add operator !or

llvm-svn: 286936

llvm/lib/TableGen/TGParser.cpp

diff --git a/llvm/lib/TableGen/TGParser.cpp b/llvm/lib/TableGen/TGParser.cpp
index 0a6752b..ff5c96b 100644
--- a/llvm/lib/TableGen/TGParser.cpp
+++ b/llvm/lib/TableGen/TGParser.cpp
@@ -881,6 +881,7 @@
   case tgtok::XConcat:
   case tgtok::XADD:
   case tgtok::XAND:
+  case tgtok::XOR:
   case tgtok::XSRA:
   case tgtok::XSRL:
   case tgtok::XSHL:
@@ -899,6 +900,7 @@
     case tgtok::XConcat: Code = BinOpInit::CONCAT;Type = DagRecTy::get(); break;
     case tgtok::XADD:    Code = BinOpInit::ADD;   Type = IntRecTy::get(); break;
     case tgtok::XAND:    Code = BinOpInit::AND;   Type = IntRecTy::get(); break;
+    case tgtok::XOR:     Code = BinOpInit::OR;    Type = IntRecTy::get(); break;
     case tgtok::XSRA:    Code = BinOpInit::SRA;   Type = IntRecTy::get(); break;
     case tgtok::XSRL:    Code = BinOpInit::SRL;   Type = IntRecTy::get(); break;
     case tgtok::XSHL:    Code = BinOpInit::SHL;   Type = IntRecTy::get(); break;
@@ -1446,6 +1448,7 @@
   case tgtok::XConcat:
   case tgtok::XADD:
   case tgtok::XAND:
+  case tgtok::XOR:
   case tgtok::XSRA:
   case tgtok::XSRL:
   case tgtok::XSHL: