[RISCV] Avoid unnecessary XOR for seteq/setne 0
Differential Revision: https://reviews.llvm.org/D53492
Patch by James Clarke.
llvm-svn: 346497
diff --git a/llvm/test/CodeGen/RISCV/i32-icmp.ll b/llvm/test/CodeGen/RISCV/i32-icmp.ll
index e115494..3b89504 100644
--- a/llvm/test/CodeGen/RISCV/i32-icmp.ll
+++ b/llvm/test/CodeGen/RISCV/i32-icmp.ll
@@ -16,6 +16,16 @@
ret i32 %2
}
+define i32 @icmp_eqz(i32 %a) nounwind {
+; RV32I-LABEL: icmp_eqz:
+; RV32I: # %bb.0:
+; RV32I-NEXT: seqz a0, a0
+; RV32I-NEXT: ret
+ %1 = icmp eq i32 %a, 0
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
define i32 @icmp_ne(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: icmp_ne:
; RV32I: # %bb.0:
@@ -27,6 +37,16 @@
ret i32 %2
}
+define i32 @icmp_nez(i32 %a) nounwind {
+; RV32I-LABEL: icmp_nez:
+; RV32I: # %bb.0:
+; RV32I-NEXT: snez a0, a0
+; RV32I-NEXT: ret
+ %1 = icmp ne i32 %a, 0
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
define i32 @icmp_ugt(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: icmp_ugt:
; RV32I: # %bb.0: