commit 1d793b8ac545344265f6ec3fa58fc37e186833a7
author Simon Pilgrim <llvm-dev@redking.me.uk> Thu Apr 05 13:11:36 2018 +0000
committer Simon Pilgrim <llvm-dev@redking.me.uk> Thu Apr 05 13:11:36 2018 +0000
tree d5a6de96bf8f053801cced8ae5530e377bbeb4db
parent 8eda4b0dc0ace4e77d781dc7d30771c256f51dbc

[SchedModel] Complete models shouldn't match against itineraries when they don't use them (PR35639)

For schedule models that don't use itineraries, checkCompleteness still checks that an instruction has a matching itinerary instead of skipping and going straight to matching the InstRWs. That doesn't seem to match what happens in TargetSchedule.cpp

This patch causes problems for a number of models that had been incorrectly flagged as complete.

Differential Revision: https://reviews.llvm.org/D43235

llvm-svn: 329280

llvm/lib/Target/AMDGPU/SISchedule.td

diff --git a/llvm/lib/Target/AMDGPU/SISchedule.td b/llvm/lib/Target/AMDGPU/SISchedule.td
index 0f02f58..7af69cb 100644
--- a/llvm/lib/Target/AMDGPU/SISchedule.td
+++ b/llvm/lib/Target/AMDGPU/SISchedule.td
@@ -46,7 +46,7 @@
 // instructions)
 
 class SISchedMachineModel : SchedMachineModel {
-  let CompleteModel = 1;
+  let CompleteModel = 0;
   // MicroOpBufferSize = 1 means that instructions will always be added
   // the ready queue when they become available.  This exposes them
   // to the register pressure analysis.

llvm/lib/Target/Mips/MipsScheduleGeneric.td

diff --git a/llvm/lib/Target/Mips/MipsScheduleGeneric.td b/llvm/lib/Target/Mips/MipsScheduleGeneric.td
index c58693c..4087f1c 100644
--- a/llvm/lib/Target/Mips/MipsScheduleGeneric.td
+++ b/llvm/lib/Target/Mips/MipsScheduleGeneric.td
@@ -25,7 +25,7 @@
   int HighLatency = 37;
   list<Predicate> UnsupportedFeatures = [];
 
-  let CompleteModel = 1;
+  let CompleteModel = 0;
   let PostRAScheduler = 1;
 
   // FIXME: Remove when all errors have been fixed.

llvm/lib/Target/Mips/MipsScheduleP5600.td

diff --git a/llvm/lib/Target/Mips/MipsScheduleP5600.td b/llvm/lib/Target/Mips/MipsScheduleP5600.td
index 9223f33..61dab40 100644
--- a/llvm/lib/Target/Mips/MipsScheduleP5600.td
+++ b/llvm/lib/Target/Mips/MipsScheduleP5600.td
@@ -13,7 +13,7 @@
   int LoadLatency = 4;
   int MispredictPenalty = 8; // TODO: Estimated
 
-  let CompleteModel = 1;
+  let CompleteModel = 0;
 
   list<Predicate> UnsupportedFeatures = [HasMips32r6, HasMips64r6,
                                          HasMips64, HasMips64r2, HasCnMips,

llvm/lib/Target/PowerPC/PPCScheduleP9.td

diff --git a/llvm/lib/Target/PowerPC/PPCScheduleP9.td b/llvm/lib/Target/PowerPC/PPCScheduleP9.td
index dbebc75..6db2a79 100644
--- a/llvm/lib/Target/PowerPC/PPCScheduleP9.td
+++ b/llvm/lib/Target/PowerPC/PPCScheduleP9.td
@@ -33,7 +33,7 @@
   // A dispatch group is 6 instructions.
   let LoopMicroOpBufferSize = 60;
 
-  let CompleteModel = 1;
+  let CompleteModel = 0;
 
   // Do not support QPX (Quad Processing eXtension) on Power 9.
   let UnsupportedFeatures = [HasQPX];

llvm/utils/TableGen/CodeGenSchedule.cpp

diff --git a/llvm/utils/TableGen/CodeGenSchedule.cpp b/llvm/utils/TableGen/CodeGenSchedule.cpp
index 5c52bdd..cc28cdf 100644
--- a/llvm/utils/TableGen/CodeGenSchedule.cpp
+++ b/llvm/utils/TableGen/CodeGenSchedule.cpp
@@ -1626,6 +1626,7 @@
   bool Complete = true;
   bool HadCompleteModel = false;
   for (const CodeGenProcModel &ProcModel : procModels()) {
+    const bool HasItineraries = ProcModel.hasItineraries();
     if (!ProcModel.ModelDef->getValueAsBit("CompleteModel"))
       continue;
     for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumValue()) {
@@ -1646,7 +1647,7 @@
       const CodeGenSchedClass &SC = getSchedClass(SCIdx);
       if (!SC.Writes.empty())
         continue;
-      if (SC.ItinClassDef != nullptr &&
+      if (HasItineraries && SC.ItinClassDef != nullptr &&
           SC.ItinClassDef->getName() != "NoItinerary")
         continue;