ARM LDRD(register) assembly parsing and encoding.
Add support for literal encoding of #-0 along the way.
llvm-svn: 137254
diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td
index 0aaf676..3b77cdb 100644
--- a/llvm/lib/Target/ARM/ARMInstrInfo.td
+++ b/llvm/lib/Target/ARM/ARMInstrInfo.td
@@ -722,7 +722,10 @@
// FIXME: split into imm vs. reg versions.
// FIXME: parser method to handle +/- register.
-def AM3OffsetAsmOperand : AsmOperandClass { let Name = "AM3Offset"; }
+def AM3OffsetAsmOperand : AsmOperandClass {
+ let Name = "AM3Offset";
+ let ParserMethod = "parseAM3Offset";
+}
def am3offset : Operand<i32>,
ComplexPattern<i32, 2, "SelectAddrMode3Offset",
[], [SDNPWantRoot]> {