commit 1daad91af695ad3fe5b15c815362af262d44584a
author Matt Arsenault <Matthew.Arsenault@amd.com> Mon Jul 01 15:23:04 2019 +0000
committer Matt Arsenault <Matthew.Arsenault@amd.com> Mon Jul 01 15:23:04 2019 +0000
tree bb008acd5ca99fdef65752c09026249930d240a7
parent fb99fc7a6893dbfe9e87f662aeea11cba7bc7e06

AMDGPU/GlobalISel: Tolerate copies with no type set

isVCC has the same bug, but isn't used in a context where it can cause
a problem.

llvm-svn: 364784

llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
index 3e7cd2d..7ea1a67 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -65,9 +65,12 @@
   auto &RegClassOrBank = MRI.getRegClassOrRegBank(Reg);
   const TargetRegisterClass *RC =
       RegClassOrBank.dyn_cast<const TargetRegisterClass*>();
-  if (RC)
-    return RC->getID() == AMDGPU::SReg_32_XM0RegClassID &&
-           MRI.getType(Reg).getSizeInBits() == 1;
+  if (RC) {
+    if (RC->getID() != AMDGPU::SReg_32_XM0RegClassID)
+      return false;
+    const LLT Ty = MRI.getType(Reg);
+    return Ty.isValid() && Ty.getSizeInBits() == 1;
+  }
 
   const RegisterBank *RB = RegClassOrBank.get<const RegisterBank *>();
   return RB->getID() == AMDGPU::SCCRegBankID;