commit 1db6d7af46276ff65dc267e7bf2d424993b95d6b
author Amjad Aboud <amjad.aboud@intel.com> Mon Oct 12 11:47:46 2015 +0000
committer Amjad Aboud <amjad.aboud@intel.com> Mon Oct 12 11:47:46 2015 +0000
tree 96e84e53a625a320e1f81aca30658f1e4b8ea206
parent 9b278a16958c7d1526eea23cdcd8f603b308ae0b

[X86] Add XSAVE intrinsic family

Add intrinsics for the
  XSAVE instructions (XSAVE/XSAVE64/XRSTOR/XRSTOR64)
  XSAVEOPT instructions (XSAVEOPT/XSAVEOPT64)
  XSAVEC instructions (XSAVEC/XSAVEC64)
  XSAVES instructions (XSAVES/XSAVES64/XRSTORS/XRSTORS64)

Differential Revision: http://reviews.llvm.org/D13012

llvm-svn: 250029

llvm/lib/Support/Host.cpp

diff --git a/llvm/lib/Support/Host.cpp b/llvm/lib/Support/Host.cpp
index cb1c82b..da91889 100644
--- a/llvm/lib/Support/Host.cpp
+++ b/llvm/lib/Support/Host.cpp
@@ -769,6 +769,7 @@
   Features["movbe"]  = (ECX >> 22) & 1;
   Features["popcnt"] = (ECX >> 23) & 1;
   Features["aes"]    = (ECX >> 25) & 1;
+  Features["xsave"]  = (ECX >> 26) & 1;
   Features["rdrnd"]  = (ECX >> 30) & 1;
 
   // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
@@ -819,6 +820,14 @@
   Features["avx512bw"] = HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save;
   Features["avx512vl"] = HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save;
 
+
+  bool HasLeafD = MaxLevel >= 0xd &&
+    !GetX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX);
+
+  Features["xsaveopt"] = Features["xsave"] && HasLeafD && ((EAX >> 0) & 1);
+  Features["xsavec"]   = Features["xsave"] && HasLeafD && ((EAX >> 1) & 1);
+  Features["xsaves"]   = Features["xsave"] && HasLeafD && ((EAX >> 3) & 1);
+
   return true;
 }
 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__))