Fix lowering of INSERT_VECTOR_ELT in SPU.
The IDX was treated as byte index, not element index.
llvm-svn: 112422
diff --git a/llvm/lib/Target/CellSPU/SPUISelLowering.cpp b/llvm/lib/Target/CellSPU/SPUISelLowering.cpp
index 53ec0ee..46f3189 100644
--- a/llvm/lib/Target/CellSPU/SPUISelLowering.cpp
+++ b/llvm/lib/Target/CellSPU/SPUISelLowering.cpp
@@ -2053,20 +2053,21 @@
SDValue IdxOp = Op.getOperand(2);
DebugLoc dl = Op.getDebugLoc();
EVT VT = Op.getValueType();
+ EVT eltVT = ValOp.getValueType();
// use 0 when the lane to insert to is 'undef'
- int64_t Idx=0;
+ int64_t Offset=0;
if (IdxOp.getOpcode() != ISD::UNDEF) {
ConstantSDNode *CN = cast<ConstantSDNode>(IdxOp);
assert(CN != 0 && "LowerINSERT_VECTOR_ELT: Index is not constant!");
- Idx = (CN->getSExtValue());
+ Offset = (CN->getSExtValue()) * eltVT.getSizeInBits()/8;
}
EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
// Use $sp ($1) because it's always 16-byte aligned and it's available:
SDValue Pointer = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT,
DAG.getRegister(SPU::R1, PtrVT),
- DAG.getConstant(Idx, PtrVT));
+ DAG.getConstant(Offset, PtrVT));
// widen the mask when dealing with half vectors
EVT maskVT = EVT::getVectorVT(*(DAG.getContext()), VT.getVectorElementType(),
128/ VT.getVectorElementType().getSizeInBits());
diff --git a/llvm/test/CodeGen/CellSPU/shuffles.ll b/llvm/test/CodeGen/CellSPU/shuffles.ll
index bc087f4..f37d2ae 100644
--- a/llvm/test/CodeGen/CellSPU/shuffles.ll
+++ b/llvm/test/CodeGen/CellSPU/shuffles.ll
@@ -31,3 +31,11 @@
ret void
}
+define <4 x float> @test_insert_1(<4 x float> %vparam, float %eltparam) {
+;CHECK: cwd $5, 4($sp)
+;CHECK: shufb $3, $4, $3, $5
+;CHECK: bi $lr
+ %rv = insertelement <4 x float> %vparam, float %eltparam, i32 1
+ ret <4 x float> %rv
+}
+