[llvm-mca] Introduce a new base class for mca::Instruction, and change how read/write information is stored.
This patch introduces a new base class for Instruction named InstructionBase.
Class InstructionBase is responsible for tracking data dependencies with the
help of ReadState and WriteState objects. Class Instruction now derives from
InstructionBase, and adds extra information related to the `InstrStage` as well
as the `RCUTokenID`.
ReadState and WriteState objects are no longer unique pointers. This avoids
extra heap allocation and pointer checks that weren't really needed. Now, those
objects are simply stored into SmallVectors. We use a SmallVector instead of a
std::vector because we expect most instructions to only have a very small number
of reads and writes. By using a simple SmallVector we also avoid extra heap
allocations most of the time.
In a debug build, this improves the performance of llvm-mca by roughly 10% (I
still have to verify the impact in performance on a release build).
llvm-svn: 345280
diff --git a/llvm/tools/llvm-mca/lib/Instruction.cpp b/llvm/tools/llvm-mca/lib/Instruction.cpp
index 511e7b2..12b6e18 100644
--- a/llvm/tools/llvm-mca/lib/Instruction.cpp
+++ b/llvm/tools/llvm-mca/lib/Instruction.cpp
@@ -120,10 +120,10 @@
Stage = IS_EXECUTING;
// Set the cycles left before the write-back stage.
- CyclesLeft = Desc.MaxLatency;
+ CyclesLeft = getLatency();
- for (UniqueDef &Def : Defs)
- Def->onInstructionIssued();
+ for (WriteState &WS : getDefs())
+ WS.onInstructionIssued();
// Transition to the "executed" stage if this is a zero-latency instruction.
if (!CyclesLeft)
@@ -139,21 +139,21 @@
void Instruction::update() {
assert(isDispatched() && "Unexpected instruction stage found!");
- if (!all_of(Uses, [](const UniqueUse &Use) { return Use->isReady(); }))
+ if (!all_of(getUses(), [](const ReadState &Use) { return Use.isReady(); }))
return;
// A partial register write cannot complete before a dependent write.
- auto IsDefReady = [&](const UniqueDef &Def) {
- if (const WriteState *Write = Def->getDependentWrite()) {
+ auto IsDefReady = [&](const WriteState &Def) {
+ if (const WriteState *Write = Def.getDependentWrite()) {
int WriteLatency = Write->getCyclesLeft();
if (WriteLatency == UNKNOWN_CYCLES)
return false;
- return static_cast<unsigned>(WriteLatency) < Desc.MaxLatency;
+ return static_cast<unsigned>(WriteLatency) < getLatency();
}
return true;
};
- if (all_of(Defs, IsDefReady))
+ if (all_of(getDefs(), IsDefReady))
Stage = IS_READY;
}
@@ -162,8 +162,8 @@
return;
if (isDispatched()) {
- for (UniqueUse &Use : Uses)
- Use->cycleEvent();
+ for (ReadState &Use : getUses())
+ Use.cycleEvent();
update();
return;
@@ -171,8 +171,8 @@
assert(isExecuting() && "Instruction not in-flight?");
assert(CyclesLeft && "Instruction already executed?");
- for (UniqueDef &Def : Defs)
- Def->cycleEvent();
+ for (WriteState &Def : getDefs())
+ Def.cycleEvent();
CyclesLeft--;
if (!CyclesLeft)
Stage = IS_EXECUTED;