[AArch64] Move feature predctrl to predres
Follow up patch of rL350385, for adding predres
command line option. This patch renames the
feature as to keep it aligned with the option
passed by/to clang
Differential Revision: https://reviews.llvm.org/D56484
llvm-svn: 350702
diff --git a/llvm/lib/Target/AArch64/AArch64.td b/llvm/lib/Target/AArch64/AArch64.td
index e6da78d..03d2830 100644
--- a/llvm/lib/Target/AArch64/AArch64.td
+++ b/llvm/lib/Target/AArch64/AArch64.td
@@ -312,8 +312,8 @@
def FeatureSSBS : SubtargetFeature<"ssbs", "HasSSBS",
"true", "Enable Speculative Store Bypass Safe bit" >;
-def FeaturePredCtrl : SubtargetFeature<"predctrl", "HasPredCtrl", "true",
- "Enable execution and data prediction invalidation instructions" >;
+def FeaturePredRes : SubtargetFeature<"predres", "HasPredRes", "true",
+ "Enable v8.5a execution and data prediction invalidation instructions" >;
def FeatureCacheDeepPersist : SubtargetFeature<"ccdp", "HasCCDP",
"true", "Enable v8.5 Cache Clean to Point of Deep Persistence" >;
@@ -352,7 +352,7 @@
def HasV8_5aOps : SubtargetFeature<
"v8.5a", "HasV8_5aOps", "true", "Support ARM v8.5a instructions",
[HasV8_4aOps, FeatureAltFPCmp, FeatureFRInt3264, FeatureSpecRestrict,
- FeatureSSBS, FeatureSB, FeaturePredCtrl, FeatureCacheDeepPersist,
+ FeatureSSBS, FeatureSB, FeaturePredRes, FeatureCacheDeepPersist,
FeatureBranchTargetId]
>;
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 67a2095..22dd198 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -116,8 +116,8 @@
AssemblerPredicate<"FeatureFRInt3264", "frint3264">;
def HasSB : Predicate<"Subtarget->hasSB()">,
AssemblerPredicate<"FeatureSB", "sb">;
-def HasPredCtrl : Predicate<"Subtarget->hasPredCtrl()">,
- AssemblerPredicate<"FeaturePredCtrl", "predctrl">;
+def HasPredRes : Predicate<"Subtarget->hasPredRes()">,
+ AssemblerPredicate<"FeaturePredRes", "predres">;
def HasCCDP : Predicate<"Subtarget->hasCCDP()">,
AssemblerPredicate<"FeatureCacheDeepPersist", "ccdp">;
def HasBTI : Predicate<"Subtarget->hasBTI()">,
diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.h b/llvm/lib/Target/AArch64/AArch64Subtarget.h
index e94a044..f2ad4b5 100644
--- a/llvm/lib/Target/AArch64/AArch64Subtarget.h
+++ b/llvm/lib/Target/AArch64/AArch64Subtarget.h
@@ -128,7 +128,7 @@
bool HasSpecRestrict = false;
bool HasSSBS = false;
bool HasSB = false;
- bool HasPredCtrl = false;
+ bool HasPredRes = false;
bool HasCCDP = false;
bool HasBTI = false;
bool HasRandGen = false;
@@ -357,7 +357,7 @@
bool hasSpecRestrict() const { return HasSpecRestrict; }
bool hasSSBS() const { return HasSSBS; }
bool hasSB() const { return HasSB; }
- bool hasPredCtrl() const { return HasPredCtrl; }
+ bool hasPredRes() const { return HasPredRes; }
bool hasCCDP() const { return HasCCDP; }
bool hasBTI() const { return HasBTI; }
bool hasRandGen() const { return HasRandGen; }
diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
index 60d48e4..a804fb1 100644
--- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
+++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
@@ -501,7 +501,7 @@
code Requires = [{ {} }];
}
-let Requires = [{ {AArch64::FeaturePredCtrl} }] in {
+let Requires = [{ {AArch64::FeaturePredRes} }] in {
def : PRCTX<"RCTX", 0b0011>;
}
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index 8876659..6cc9b67 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -2826,7 +2826,7 @@
{"simd", {AArch64::FeatureNEON}},
{"ras", {AArch64::FeatureRAS}},
{"lse", {AArch64::FeatureLSE}},
- {"predctrl", {AArch64::FeaturePredCtrl}},
+ {"predres", {AArch64::FeaturePredRes}},
{"ccdp", {AArch64::FeatureCacheDeepPersist}},
{"mte", {AArch64::FeatureMTE}},
{"tlb-rmi", {AArch64::FeatureTLB_RMI}},