commit 1ed771f5d7e68c868807f3b59e18f36dd50b0fbf
author Sanjay Patel <spatel@rotateright.com> Wed Sep 14 16:37:15 2016 +0000
committer Sanjay Patel <spatel@rotateright.com> Wed Sep 14 16:37:15 2016 +0000
tree 34e0f93dcb6c1ef93d20f2b037cb470f8634215c
parent d10a5ea19ece4b5d77fb548c04b782966de873a7

getVectorElementType().getSizeInBits() -> getScalarSizeInBits() ; NFCI

llvm-svn: 281495

llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp

diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
index f0a5534..b00b58c 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
@@ -816,7 +816,7 @@
     SDNode *Mask = CurDAG->getMachineNode(Hexagon::C2_mask, dl, MVT::i64, Op0);
     unsigned NE = OpVT.getVectorNumElements();
     EVT ExVT = N->getValueType(0);
-    unsigned ES = ExVT.getVectorElementType().getSizeInBits();
+    unsigned ES = ExVT.getScalarSizeInBits();
     uint64_t MV = 0, Bit = 1;
     for (unsigned i = 0; i < NE; ++i) {
       MV |= Bit;

llvm/lib/Target/Hexagon/HexagonISelLowering.cpp

diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
index 75a19ed..5a6721b 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
@@ -2389,7 +2389,7 @@
   if (UseHVX) {
     ArrayRef<int> Mask = SVN->getMask();
     size_t MaskLen = Mask.size();
-    int ElemSizeInBits = VT.getVectorElementType().getSizeInBits();
+    int ElemSizeInBits = VT.getScalarSizeInBits();
     if ((Subtarget.useHVXSglOps() && (ElemSizeInBits * MaskLen) == 64 * 8) ||
         (Subtarget.useHVXDblOps() && (ElemSizeInBits * MaskLen) == 128 * 8)) {
       // Return 1 for odd and 2 of even