[AArch64] Optimise load(adr address) to ldr address
Providing that the load is known to be 4 byte aligned, we can optimise a
ldr(adr address) to just ldr address.
Differential Revision: https://reviews.llvm.org/D51030
llvm-svn: 341058
diff --git a/llvm/test/CodeGen/AArch64/tiny_model.ll b/llvm/test/CodeGen/AArch64/tiny_model.ll
index ecf0d76..953aa37 100644
--- a/llvm/test/CodeGen/AArch64/tiny_model.ll
+++ b/llvm/test/CodeGen/AArch64/tiny_model.ll
@@ -89,9 +89,8 @@
; CHECK-LABEL: foo3:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: adr x8, src
-; CHECK-NEXT: adr x9, ptr
; CHECK-NEXT: ldrb w8, [x8]
-; CHECK-NEXT: ldr x9, [x9]
+; CHECK-NEXT: ldr x9, ptr
; CHECK-NEXT: strb w8, [x9]
; CHECK-NEXT: ret
;
@@ -209,9 +208,8 @@
; CHECK-LABEL: bar3:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: adr x8, lsrc
-; CHECK-NEXT: adr x9, lptr
; CHECK-NEXT: ldrb w8, [x8]
-; CHECK-NEXT: ldr x9, [x9]
+; CHECK-NEXT: ldr x9, lptr
; CHECK-NEXT: strb w8, [x9]
; CHECK-NEXT: ret
;
@@ -227,9 +225,8 @@
; CHECK-PIC-LABEL: bar3:
; CHECK-PIC: // %bb.0: // %entry
; CHECK-PIC-NEXT: adr x8, lsrc
-; CHECK-PIC-NEXT: adr x9, lptr
; CHECK-PIC-NEXT: ldrb w8, [x8]
-; CHECK-PIC-NEXT: ldr x9, [x9]
+; CHECK-PIC-NEXT: ldr x9, lptr
; CHECK-PIC-NEXT: strb w8, [x9]
; CHECK-PIC-NEXT: ret
;
@@ -329,9 +326,8 @@
; CHECK-LABEL: baz3:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: adr x8, lbsrc
-; CHECK-NEXT: adr x9, lptr
; CHECK-NEXT: ldrb w8, [x8]
-; CHECK-NEXT: ldr x9, [x9]
+; CHECK-NEXT: ldr x9, lptr
; CHECK-NEXT: strb w8, [x9]
; CHECK-NEXT: ret
;
@@ -347,9 +343,8 @@
; CHECK-PIC-LABEL: baz3:
; CHECK-PIC: // %bb.0: // %entry
; CHECK-PIC-NEXT: adr x8, lbsrc
-; CHECK-PIC-NEXT: adr x9, lptr
; CHECK-PIC-NEXT: ldrb w8, [x8]
-; CHECK-PIC-NEXT: ldr x9, [x9]
+; CHECK-PIC-NEXT: ldr x9, lptr
; CHECK-PIC-NEXT: strb w8, [x9]
; CHECK-PIC-NEXT: ret
;