[SPARC] Switch to the Machine Scheduler.
The (mostly-deprecated) SelectionDAG-based ILPListDAGScheduler scheduler
was making poor scheduling decisions, causing high register pressure and
extraneous register spills.
Switching to the newer machine scheduler generates better code -- even
without there being a machine model defined for SPARC yet.
(Actually committing the test changes too, this time, unlike r247315)
llvm-svn: 247343
diff --git a/llvm/test/CodeGen/SPARC/float.ll b/llvm/test/CodeGen/SPARC/float.ll
index d7a79cb..c4cc044 100644
--- a/llvm/test/CodeGen/SPARC/float.ll
+++ b/llvm/test/CodeGen/SPARC/float.ll
@@ -53,20 +53,18 @@
declare double @llvm.fabs.f64(double) nounwind readonly
; V8-LABEL: test_v9_floatreg:
-; V8: fsubd {{.+}}, {{.+}}, {{.+}}
-; V8: faddd {{.+}}, {{.+}}, [[R:%f(((1|2)?(0|2|4|6|8))|30)]]
+; V8: fsubd {{.+}}, {{.+}}, [[R:%f(((1|2)?(0|2|4|6|8))|30)]]
; V8: std [[R]], [%{{.+}}]
; V8: ldd [%{{.+}}], %f0
+; V8: faddd {{.+}}, {{.+}}, {{.+}}
; V9-LABEL: test_v9_floatreg:
; V9: fsubd {{.+}}, {{.+}}, {{.+}}
-; V9: faddd {{.+}}, {{.+}}, [[R:%f((3(2|4|6|8))|((4|5)(0|2|4|6|8))|(60|62))]]
-; V9: fmovd [[R]], %f0
+; V9: faddd {{.+}}, {{.+}}, %f0
; SPARC64-LABEL: test_v9_floatreg:
; SPARC64: fsubd {{.+}}, {{.+}}, {{.+}}
-; SPARC64: faddd {{.+}}, {{.+}}, [[R:%f((3(2|4|6|8))|((4|5)(0|2|4|6|8))|(60|62))]]
-; SPARC64: fmovd [[R]], %f0
+; SPARC64: faddd {{.+}}, {{.+}}, %f0
define double @test_v9_floatreg() {
entry: