commit 1f5178ff9f09f4b82f2eb3015fc3e15ac5610df0
author Craig Topper <craig.topper@gmail.com> Mon Oct 17 06:41:18 2016 +0000
committer Craig Topper <craig.topper@gmail.com> Mon Oct 17 06:41:18 2016 +0000
tree 05552a8634ac80e5e050d7e0e1c875df479fa65f
parent 9f9eee015216a19ba1c45462254c905cd9e62db9

[X86] Fix shuffle decoding assertions to print the right number of required operands. Update the checks themselves to be >= to the same number instead of > one less than the required number.

llvm-svn: 284365

llvm/lib/Target/X86/X86MCInstLower.cpp

diff --git a/llvm/lib/Target/X86/X86MCInstLower.cpp b/llvm/lib/Target/X86/X86MCInstLower.cpp
index 8f46168..25a9cd0 100644
--- a/llvm/lib/Target/X86/X86MCInstLower.cpp
+++ b/llvm/lib/Target/X86/X86MCInstLower.cpp
@@ -1534,8 +1534,8 @@
   case X86::VPERMILPDZrm: {
     if (!OutStreamer->isVerboseAsm())
       break;
-    assert(MI->getNumOperands() > 5 &&
-           "We should always have at least 5 operands!");
+    assert(MI->getNumOperands() >= 6 &&
+           "We should always have at least 6 operands!");
     const MachineOperand &DstOp = MI->getOperand(0);
     const MachineOperand &SrcOp = MI->getOperand(1);
     const MachineOperand &MaskOp = MI->getOperand(5);
@@ -1556,8 +1556,8 @@
   case X86::VPERMILPSZrm: {
     if (!OutStreamer->isVerboseAsm())
       break;
-    assert(MI->getNumOperands() > 5 &&
-           "We should always have at least 5 operands!");
+    assert(MI->getNumOperands() >= 6 &&
+           "We should always have at least 6 operands!");
     const MachineOperand &DstOp = MI->getOperand(0);
     const MachineOperand &SrcOp = MI->getOperand(1);
     const MachineOperand &MaskOp = MI->getOperand(5);
@@ -1577,8 +1577,8 @@
   case X86::VPERMIL2PSrmY: {
     if (!OutStreamer->isVerboseAsm())
       break;
-    assert(MI->getNumOperands() > 7 &&
-      "We should always have at least 7 operands!");
+    assert(MI->getNumOperands() >= 8 &&
+           "We should always have at least 8 operands!");
     const MachineOperand &DstOp = MI->getOperand(0);
     const MachineOperand &SrcOp1 = MI->getOperand(1);
     const MachineOperand &SrcOp2 = MI->getOperand(2);
@@ -1607,8 +1607,8 @@
   case X86::VPPERMrrm: {
     if (!OutStreamer->isVerboseAsm())
       break;
-    assert(MI->getNumOperands() > 6 &&
-           "We should always have at least 6 operands!");
+    assert(MI->getNumOperands() >= 7 &&
+           "We should always have at least 7 operands!");
     const MachineOperand &DstOp = MI->getOperand(0);
     const MachineOperand &SrcOp1 = MI->getOperand(1);
     const MachineOperand &SrcOp2 = MI->getOperand(2);