commit 1f9939fba634f297acb00f936d6a55bdf8b00e69
author Tom Stellard <thomas.stellard@amd.com> Fri Feb 27 14:59:41 2015 +0000
committer Tom Stellard <thomas.stellard@amd.com> Fri Feb 27 14:59:41 2015 +0000
tree 534450d097a67b1077597b23017e40037f385415
parent 1df918083cd05b78c0bad87af8b6429ab4887cce

R600/SI: Add slc, glc, and tfe to non-atomic _ADDR64 instructions

llvm-svn: 230757

llvm/lib/Target/R600/SIInstructions.td

diff --git a/llvm/lib/Target/R600/SIInstructions.td b/llvm/lib/Target/R600/SIInstructions.td
index 4f72e99..95b8de9 100644
--- a/llvm/lib/Target/R600/SIInstructions.td
+++ b/llvm/lib/Target/R600/SIInstructions.td
@@ -2898,8 +2898,9 @@
 multiclass MUBUFLoad_Pattern <MUBUF Instr_ADDR64, ValueType vt,
                               PatFrag constant_ld> {
   def : Pat <
-     (vt (constant_ld (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset, i16:$offset))),
-     (Instr_ADDR64 $srsrc, $vaddr, $soffset, $offset)
+     (vt (constant_ld (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset,
+                                   i16:$offset, i1:$glc, i1:$slc, i1:$tfe))),
+     (Instr_ADDR64 $srsrc, $vaddr, $soffset, $offset, $glc, $slc, $tfe)
   >;
 }