commit 20f62070132cf4a4d3273594f1dea02e3d41e6f8
author Aditya Nandakumar <aditya_nandakumar@apple.com> Thu Jun 29 23:43:44 2017 +0000
committer Aditya Nandakumar <aditya_nandakumar@apple.com> Thu Jun 29 23:43:44 2017 +0000
tree ebaa7a959e1524817941d9c7a42745e3926f9ae6
parent 0a94072e4d577397a989aa056c36f70f64fbba24

[GISel]: New Opcode G_FLOG/G_FLOG2

https://reviews.llvm.org/D34837

llvm-svn: 306766

llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp

diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index fcaa1fb..521037f 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -730,6 +730,16 @@
         .addDef(getOrCreateVReg(CI))
         .addUse(getOrCreateVReg(*CI.getArgOperand(0)));
     return true;
+  case Intrinsic::log:
+    MIRBuilder.buildInstr(TargetOpcode::G_FLOG)
+        .addDef(getOrCreateVReg(CI))
+        .addUse(getOrCreateVReg(*CI.getArgOperand(0)));
+    return true;
+  case Intrinsic::log2:
+    MIRBuilder.buildInstr(TargetOpcode::G_FLOG2)
+        .addDef(getOrCreateVReg(CI))
+        .addUse(getOrCreateVReg(*CI.getArgOperand(0)));
+    return true;
   case Intrinsic::fma:
     MIRBuilder.buildInstr(TargetOpcode::G_FMA)
         .addDef(getOrCreateVReg(CI))