[ARM] Enable useAA() for the in-order Cortex-R52
This option allows codegen (such as DAGCombine or MI scheduling) to use alias
analysis information, which can help with the codegen on in-order cpu's,
especially machine scheduling. Here I have done things the same way as AArch64,
adding a subtarget feature to enable this for specific cores, and enabled it for
the R52 where we have a schedule to make use of it.
Differential Revision: https://reviews.llvm.org/D48074
llvm-svn: 335249
diff --git a/llvm/lib/Target/ARM/ARM.td b/llvm/lib/Target/ARM/ARM.td
index 2c3587e..7b551c4 100644
--- a/llvm/lib/Target/ARM/ARM.td
+++ b/llvm/lib/Target/ARM/ARM.td
@@ -330,6 +330,10 @@
"DisablePostRAScheduler", "true",
"Don't schedule again after register allocation">;
+// Enable use of alias analysis during code generation
+def FeatureUseAA : SubtargetFeature<"use-aa", "UseAA", "true",
+ "Use alias analysis during codegen">;
+
//===----------------------------------------------------------------------===//
// ARM architecture class
//
@@ -1006,7 +1010,8 @@
def : ProcessorModel<"cortex-r52", CortexR52Model, [ARMv8r, ProcR52,
FeatureUseMISched,
- FeatureFPAO]>;
+ FeatureFPAO,
+ FeatureUseAA]>;
//===----------------------------------------------------------------------===//
// Register File Description
diff --git a/llvm/lib/Target/ARM/ARMSubtarget.h b/llvm/lib/Target/ARM/ARMSubtarget.h
index e23a5fe..f72b97f 100644
--- a/llvm/lib/Target/ARM/ARMSubtarget.h
+++ b/llvm/lib/Target/ARM/ARMSubtarget.h
@@ -198,6 +198,9 @@
/// register allocation.
bool DisablePostRAScheduler = false;
+ /// UseAA - True if using AA during codegen (DAGCombine, MISched, etc)
+ bool UseAA = false;
+
/// HasThumb2 - True if Thumb2 instructions are supported.
bool HasThumb2 = false;
@@ -723,6 +726,10 @@
/// True for some subtargets at > -O0.
bool enablePostRAScheduler() const override;
+ /// Enable use of alias analysis during code generation (during MI
+ /// scheduling, DAGCombine, etc.).
+ bool useAA() const override { return UseAA; }
+
// enableAtomicExpand- True if we need to expand our atomics.
bool enableAtomicExpand() const override;