IntegerRegSize is always 8 for sparc
llvm-svn: 5961
diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.cpp b/llvm/lib/Target/Sparc/SparcInstrInfo.cpp
index 8bdb0f2..331fd46 100644
--- a/llvm/lib/Target/Sparc/SparcInstrInfo.cpp
+++ b/llvm/lib/Target/Sparc/SparcInstrInfo.cpp
@@ -441,9 +441,7 @@
uint64_t C = GetConstantValueAsUnsignedInt(val, isValidConstant);
assert(isValidConstant && "Unrecognized constant");
- if (opSize > destSize ||
- (val->getType()->isSigned()
- && destSize < target.getTargetData().getIntegerRegSize()))
+ if (opSize > destSize || (val->getType()->isSigned() && destSize < 8))
{ // operand is larger than dest,
// OR both are equal but smaller than the full register size
// AND operand is signed, so it may have extra sign bits:
diff --git a/llvm/lib/Target/Sparc/SparcInstrSelection.cpp b/llvm/lib/Target/Sparc/SparcInstrSelection.cpp
index 50e2fe2..78fb2f2 100644
--- a/llvm/lib/Target/Sparc/SparcInstrSelection.cpp
+++ b/llvm/lib/Target/Sparc/SparcInstrSelection.cpp
@@ -758,8 +758,7 @@
//
Value* shiftDest = destVal;
unsigned opSize = target.getTargetData().getTypeSize(argVal1->getType());
- if ((shiftOpCode == SLL || shiftOpCode == SLLX)
- && opSize < target.getTargetData().getIntegerRegSize())
+ if ((shiftOpCode == SLL || shiftOpCode == SLLX) && opSize < 8)
{ // put SLL result into a temporary
shiftDest = new TmpInstruction(argVal1, optArgVal2, "sllTmp");
mcfi.addTemp(shiftDest);
@@ -2305,7 +2304,7 @@
.addReg(dest, MOTy::Def);
mvec.push_back(M);
}
- else if (destSize < target.getTargetData().getIntegerRegSize())
+ else if (destSize < 8)
assert(0 && "Unsupported type size: 32 < size < 64 bits");
}
}