Reverting r281719, this is causing buildbot failures and timeouts again.
llvm-svn: 281722
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 619264f..8a864c2 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -12434,24 +12434,6 @@
bool isSigned = (Opcode == ISD::SDIVREM);
EVT VT = Op->getValueType(0);
Type *Ty = VT.getTypeForEVT(*DAG.getContext());
- SDLoc dl(Op);
-
- // If the target has hardware divide, use divide + multiply + subtract:
- // div = a / b
- // rem = a - b * div
- // return {div, rem}
- // This should be lowered into UDIV/SDIV + MLS later on.
- if (Subtarget->hasDivide()) {
- unsigned DivOpcode = isSigned ? ISD::SDIV : ISD::UDIV;
- const SDValue Dividend = Op->getOperand(0);
- const SDValue Divisor = Op->getOperand(1);
- SDValue Div = DAG.getNode(DivOpcode, dl, VT, Dividend, Divisor);
- SDValue Mul = DAG.getNode(ISD::MUL, dl, VT, Div, Divisor);
- SDValue Rem = DAG.getNode(ISD::SUB, dl, VT, Dividend, Mul);
-
- SDValue Values[2] = {Div, Rem};
- return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(VT, VT), Values);
- }
RTLIB::Libcall LC = getDivRemLibcall(Op.getNode(),
VT.getSimpleVT().SimpleTy);
@@ -12465,6 +12447,7 @@
Type *RetTy = (Type*)StructType::get(Ty, Ty, nullptr);
+ SDLoc dl(Op);
TargetLowering::CallLoweringInfo CLI(DAG);
CLI.setDebugLoc(dl).setChain(InChain)
.setCallee(getLibcallCallingConv(LC), RetTy, Callee, std::move(Args))