[Hexagon] Generate COPY/REG_SEQUENCE more aggressively for vectors
llvm-svn: 277626
diff --git a/llvm/test/CodeGen/Hexagon/combine.ll b/llvm/test/CodeGen/Hexagon/combine.ll
index 8f5cec8..04a080f 100644
--- a/llvm/test/CodeGen/Hexagon/combine.ll
+++ b/llvm/test/CodeGen/Hexagon/combine.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=hexagon -mcpu=hexagonv5 -disable-hsdr < %s | FileCheck %s
+; RUN: llc -march=hexagon -mcpu=hexagonv5 -disable-hsdr -hexagon-bit=0 < %s | FileCheck %s
; CHECK: combine(r{{[0-9]+}}, r{{[0-9]+}})
@j = external global i32