Remove a register class that can just as well be synthesized.
Add the new TableGen register class synthesizer feature to the release
notes.
llvm-svn: 146875
diff --git a/llvm/docs/ReleaseNotes.html b/llvm/docs/ReleaseNotes.html
index dbeba16..6159628 100644
--- a/llvm/docs/ReleaseNotes.html
+++ b/llvm/docs/ReleaseNotes.html
@@ -337,7 +337,10 @@
make it run faster:</p>
<ul>
- <li>....</li>
+ <li>TableGen can now synthesize register classes that are only needed to
+ represent combinations of constraints from instructions and sub-registers.
+ The synthetic register classes inherit most of their properties form their
+ closest user-defined super-class.</li>
</ul>
</div>
diff --git a/llvm/lib/Target/ARM/ARMRegisterInfo.td b/llvm/lib/Target/ARM/ARMRegisterInfo.td
index 036822d..2035b65 100644
--- a/llvm/lib/Target/ARM/ARMRegisterInfo.td
+++ b/llvm/lib/Target/ARM/ARMRegisterInfo.td
@@ -326,14 +326,6 @@
let AltOrderSelect = [{ return 1; }];
}
-// Subset of QQPR that have 32-bit SPR subregs.
-def QQPR_VFP2 : RegisterClass<"ARM", [v4i64], 256, (trunc QQPR, 4)> {
- let SubRegClasses = [(SPR ssub_0, ssub_1, ssub_2, ssub_3),
- (DPR_VFP2 dsub_0, dsub_1, dsub_2, dsub_3),
- (QPR_VFP2 qsub_0, qsub_1)];
-
-}
-
// Pseudo 512-bit vector register class to model 4 consecutive Q registers
// (8 consecutive D registers).
def QQQQPR : RegisterClass<"ARM", [v8i64], 256, (sequence "QQQQ%u", 0, 3)> {