commit 24b975dc66abac4e92c79c950a32f6b67e47887c
author Hrvoje Varga <Hrvoje.Varga@imgtec.com> Mon Jun 27 08:23:28 2016 +0000
committer Hrvoje Varga <Hrvoje.Varga@imgtec.com> Mon Jun 27 08:23:28 2016 +0000
tree a7f5135cc61266818ec2d84e429a45a6d4218779
parent e5d277923a80017dec16f0d65a793a59b80bc4c7

[mips][micromips] Implement LD, LLD, LWU, SD, DSRL, DSRL32 and DSRLV instructions
Differential Revision: http://reviews.llvm.org/D16625

llvm-svn: 273850

llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp

diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
index 711e548..61b5378 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
@@ -81,6 +81,9 @@
   case Mips::DSLL_MM64R6:
     Inst.setOpcode(Mips::DSLL32_MM64R6);
     return;
+  case Mips::DSRL_MM64R6:
+    Inst.setOpcode(Mips::DSRL32_MM64R6);
+    return;
   case Mips::DSRA_MM64R6:
     Inst.setOpcode(Mips::DSRA32_MM64R6);
     return;
@@ -195,6 +198,7 @@
   case Mips::DSRA:
   case Mips::DROTR:
   case Mips::DSLL_MM64R6:
+  case Mips::DSRL_MM64R6:
   case Mips::DSRA_MM64R6:
   case Mips::DROTR_MM64R6:
     LowerLargeShift(TmpInst);