| commit | 24d9b13b36bdd14a4bc7ad29f6715bd9ebbdfed8 | [log] [tgz] |
|---|---|---|
| author | Alex Bradbury <asb@lowrisc.org> | Tue Nov 01 23:40:28 2016 +0000 |
| committer | Alex Bradbury <asb@lowrisc.org> | Tue Nov 01 23:40:28 2016 +0000 |
| tree | 0664031c76134b7f76fa2c18bbf1277c474f9f9d | |
| parent | c507cdb4bca79c6a82061c114c1d0d6e6eee73a1 [diff] |
[RISCV 4/10] Add basic RISCV{InstrFormats,InstrInfo,RegisterInfo,}.td
For now, only add instruction definitions for basic ALU operations. Our
initial target is a working MC layer rather than codegen, so appropriate
SelectionDAG patterns will come later.
Differential Revision: https://reviews.llvm.org/D23561
llvm-svn: 285769