[CodeGen] Unify MBB reference format in both MIR and debug output
As part of the unification of the debug format and the MIR format, print
MBB references as '%bb.5'.
The MIR printer prints the IR name of a MBB only for block definitions.
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g'
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g'
* find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g'
* grep -nr 'BB#' and fix
Differential Revision: https://reviews.llvm.org/D40422
llvm-svn: 319665
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
index 7362bd8..e786832 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
@@ -58,19 +58,19 @@
; CHECK: body:
;
; ABI/constant lowering and IR-level entry basic block.
-; CHECK: {{bb.[0-9]+}}.entry:
+; CHECK: bb.{{[0-9]+}}.{{[a-zA-Z0-9.]+}}:
;
; Make sure we have one successor and only one.
-; CHECK-NEXT: successors: %[[BB2:bb.[0-9]+.bb2]](0x80000000)
+; CHECK-NEXT: successors: %[[BB2:bb.[0-9]+]](0x80000000)
;
; Check that we emit the correct branch.
; CHECK: G_BR %[[BB2]]
;
; Check that end contains the return instruction.
-; CHECK: [[END:bb.[0-9]+.end]]:
+; CHECK: [[END:bb.[0-9]+]].{{[a-zA-Z0-9.]+}}:
; CHECK-NEXT: RET_ReallyLR
;
-; CHECK: {{bb.[0-9]+}}.bb2:
+; CHECK: bb.{{[0-9]+}}.{{[a-zA-Z0-9.]+}}:
; CHECK-NEXT: successors: %[[END]](0x80000000)
; CHECK: G_BR %[[END]]
define void @uncondbr() {
@@ -84,11 +84,11 @@
; CHECK-LABEL: name: uncondbr_fallthrough
; CHECK: body:
-; CHECK: {{bb.[0-9]+}}.entry:
-; CHECK-NEXT: successors: %[[END:bb.[0-9]+.end]](0x80000000)
+; CHECK: bb.{{[0-9]+}}.{{[a-zA-Z0-9.]+}}:
+; CHECK-NEXT: successors: %[[END:bb.[0-9]+]](0x80000000)
; We don't emit a branch here, as we can fallthrough to the successor.
; CHECK-NOT: G_BR
-; CHECK: [[END]]:
+; CHECK: [[END]].{{[a-zA-Z0-9.]+}}:
; CHECK-NEXT: RET_ReallyLR
define void @uncondbr_fallthrough() {
entry:
@@ -102,10 +102,10 @@
; CHECK: body:
;
; ABI/constant lowering and IR-level entry basic block.
-; CHECK: {{bb.[0-9]+}} (%ir-block.{{[0-9]+}}):
+; CHECK: bb.{{[0-9]+}} (%ir-block.{{[0-9]+}}):
; Make sure we have two successors
-; CHECK-NEXT: successors: %[[TRUE:bb.[0-9]+.true]](0x40000000),
-; CHECK: %[[FALSE:bb.[0-9]+.false]](0x40000000)
+; CHECK-NEXT: successors: %[[TRUE:bb.[0-9]+]](0x40000000),
+; CHECK: %[[FALSE:bb.[0-9]+]](0x40000000)
;
; CHECK: [[ADDR:%.*]]:_(p0) = COPY %x0
;
@@ -115,9 +115,9 @@
; CHECK: G_BR %[[FALSE]]
;
; Check that each successor contains the return instruction.
-; CHECK: [[TRUE]]:
+; CHECK: [[TRUE]].{{[a-zA-Z0-9.]+}}:
; CHECK-NEXT: RET_ReallyLR
-; CHECK: [[FALSE]]:
+; CHECK: [[FALSE]].{{[a-zA-Z0-9.]+}}:
; CHECK-NEXT: RET_ReallyLR
define void @condbr(i1* %tstaddr) {
%tst = load i1, i1* %tstaddr
@@ -133,8 +133,8 @@
; CHECK-LABEL: name: switch
; CHECK: body:
;
-; CHECK: {{bb.[0-9]+.entry}}:
-; CHECK-NEXT: successors: %[[BB_CASE100:bb.[0-9]+.case100]](0x40000000), %[[BB_NOTCASE100_CHECKNEXT:bb.[0-9]+.entry]](0x40000000)
+; CHECK: bb.{{[a-zA-Z0-9.]+}}:
+; CHECK-NEXT: successors: %[[BB_CASE100:bb.[0-9]+]](0x40000000), %[[BB_NOTCASE100_CHECKNEXT:bb.[0-9]+]](0x40000000)
; CHECK: %0:_(s32) = COPY %w0
; CHECK: %[[reg100:[0-9]+]]:_(s32) = G_CONSTANT i32 100
; CHECK: %[[reg200:[0-9]+]]:_(s32) = G_CONSTANT i32 200
@@ -145,31 +145,31 @@
; CHECK: G_BRCOND %[[regicmp100]](s1), %[[BB_CASE100]]
; CHECK: G_BR %[[BB_NOTCASE100_CHECKNEXT]]
;
-; CHECK: [[BB_NOTCASE100_CHECKNEXT]]:
-; CHECK-NEXT: successors: %[[BB_CASE200:bb.[0-9]+.case200]](0x40000000), %[[BB_NOTCASE200_CHECKNEXT:bb.[0-9]+.entry]](0x40000000)
+; CHECK: [[BB_NOTCASE100_CHECKNEXT]].{{[a-zA-Z0-9.]+}}:
+; CHECK-NEXT: successors: %[[BB_CASE200:bb.[0-9]+]](0x40000000), %[[BB_NOTCASE200_CHECKNEXT:bb.[0-9]+]](0x40000000)
; CHECK: %[[regicmp200:[0-9]+]]:_(s1) = G_ICMP intpred(eq), %[[reg200]](s32), %0
; CHECK: G_BRCOND %[[regicmp200]](s1), %[[BB_CASE200]]
; CHECK: G_BR %[[BB_NOTCASE200_CHECKNEXT]]
;
-; CHECK: [[BB_NOTCASE200_CHECKNEXT]]:
-; CHECK-NEXT: successors: %[[BB_DEFAULT:bb.[0-9]+.default]](0x80000000)
+; CHECK: [[BB_NOTCASE200_CHECKNEXT]].{{[a-zA-Z0-9.]+}}:
+; CHECK-NEXT: successors: %[[BB_DEFAULT:bb.[0-9]+]](0x80000000)
; CHECK: G_BR %[[BB_DEFAULT]]
;
-; CHECK: [[BB_DEFAULT]]:
-; CHECK-NEXT: successors: %[[BB_RET:bb.[0-9]+.return]](0x80000000)
+; CHECK: [[BB_DEFAULT]].{{[a-zA-Z0-9.]+}}:
+; CHECK-NEXT: successors: %[[BB_RET:bb.[0-9]+]](0x80000000)
; CHECK: %[[regretdefault:[0-9]+]]:_(s32) = G_ADD %0, %[[reg0]]
; CHECK: G_BR %[[BB_RET]]
;
-; CHECK: [[BB_CASE100]]:
-; CHECK-NEXT: successors: %[[BB_RET:bb.[0-9]+.return]](0x80000000)
+; CHECK: [[BB_CASE100]].{{[a-zA-Z0-9.]+}}:
+; CHECK-NEXT: successors: %[[BB_RET:bb.[0-9]+]](0x80000000)
; CHECK: %[[regretc100:[0-9]+]]:_(s32) = G_ADD %0, %[[reg1]]
; CHECK: G_BR %[[BB_RET]]
;
-; CHECK: [[BB_CASE200]]:
+; CHECK: [[BB_CASE200]].{{[a-zA-Z0-9.]+}}:
; CHECK-NEXT: successors: %[[BB_RET]](0x80000000)
; CHECK: %[[regretc200:[0-9]+]]:_(s32) = G_ADD %0, %[[reg2]]
;
-; CHECK: [[BB_RET]]:
+; CHECK: [[BB_RET]].{{[a-zA-Z0-9.]+}}:
; CHECK-NEXT: %[[regret:[0-9]+]]:_(s32) = G_PHI %[[regretdefault]](s32), %[[BB_DEFAULT]], %[[regretc100]](s32), %[[BB_CASE100]]
; CHECK: %w0 = COPY %[[regret]](s32)
; CHECK: RET_ReallyLR implicit %w0
@@ -202,16 +202,16 @@
; %entry block is no longer a predecessor for the phi instruction. We need to
; use the correct lowered MachineBasicBlock instead.
; CHECK-LABEL: name: test_cfg_remap
-; CHECK: {{bb.[0-9]+.entry}}:
-; CHECK-NEXT: successors: %{{bb.[0-9]+.next}}(0x40000000), %[[NOTCASE1_BLOCK:bb.[0-9]+.entry]](0x40000000)
-; CHECK: [[NOTCASE1_BLOCK]]:
-; CHECK-NEXT: successors: %{{bb.[0-9]+.other}}(0x40000000), %[[NOTCASE57_BLOCK:bb.[0-9]+.entry]](0x40000000)
-; CHECK: [[NOTCASE57_BLOCK]]:
-; CHECK-NEXT: successors: %[[PHI_BLOCK:bb.[0-9]+.phi.block]](0x80000000)
+; CHECK: bb.{{[0-9]+.[a-zA-Z0-9.]+}}:
+; CHECK-NEXT: successors: %{{bb.[0-9]+}}(0x40000000), %[[NOTCASE1_BLOCK:bb.[0-9]+]](0x40000000)
+; CHECK: [[NOTCASE1_BLOCK]].{{[a-zA-Z0-9.]+}}:
+; CHECK-NEXT: successors: %{{bb.[0-9]+}}(0x40000000), %[[NOTCASE57_BLOCK:bb.[0-9]+]](0x40000000)
+; CHECK: [[NOTCASE57_BLOCK]].{{[a-zA-Z0-9.]+}}:
+; CHECK-NEXT: successors: %[[PHI_BLOCK:bb.[0-9]+]](0x80000000)
; CHECK: G_BR %[[PHI_BLOCK]]
;
-; CHECK: [[PHI_BLOCK]]:
-; CHECK-NEXT: G_PHI %{{.*}}(s32), %[[NOTCASE57_BLOCK:bb.[0-9]+.entry]], %{{.*}}(s32),
+; CHECK: [[PHI_BLOCK]].{{[a-zA-Z0-9.]+}}:
+; CHECK-NEXT: G_PHI %{{.*}}(s32), %[[NOTCASE57_BLOCK:bb.[0-9]+]], %{{.*}}(s32),
;
define i32 @test_cfg_remap(i32 %in) {
entry:
@@ -230,7 +230,7 @@
}
; CHECK-LABEL: name: test_cfg_remap_multiple_preds
-; CHECK: G_PHI [[ENTRY:%.*]](s32), %bb.{{[0-9]+}}.entry, [[ENTRY]](s32), %bb.{{[0-9]+}}.entry
+; CHECK: G_PHI [[ENTRY:%.*]](s32), %bb.{{[0-9]+}}, [[ENTRY]](s32), %bb.{{[0-9]+}}
define i32 @test_cfg_remap_multiple_preds(i32 %in) {
entry:
switch i32 %in, label %odd [i32 1, label %next
@@ -256,19 +256,19 @@
; CHECK: body:
;
; ABI/constant lowering and IR-level entry basic block.
-; CHECK: {{bb.[0-9]+.entry}}:
+; CHECK: bb.{{[0-9]+.[a-zA-Z0-9.]+}}:
; Make sure we have one successor
-; CHECK-NEXT: successors: %[[BB_L1:bb.[0-9]+.L1]](0x80000000)
+; CHECK-NEXT: successors: %[[BB_L1:bb.[0-9]+]](0x80000000)
; CHECK-NOT: G_BR
;
; Check basic block L1 has 2 successors: BBL1 and BBL2
-; CHECK: [[BB_L1]] (address-taken):
+; CHECK: [[BB_L1]].{{[a-zA-Z0-9.]+}} (address-taken):
; CHECK-NEXT: successors: %[[BB_L1]](0x40000000),
-; CHECK: %[[BB_L2:bb.[0-9]+.L2]](0x40000000)
+; CHECK: %[[BB_L2:bb.[0-9]+]](0x40000000)
; CHECK: G_BRINDIRECT %{{[0-9]+}}(p0)
;
; Check basic block L2 is the return basic block
-; CHECK: [[BB_L2]] (address-taken):
+; CHECK: [[BB_L2]].{{[a-zA-Z0-9.]+}} (address-taken):
; CHECK-NEXT: RET_ReallyLR
@indirectbr.L = internal unnamed_addr constant [3 x i8*] [i8* blockaddress(@indirectbr, %L1), i8* blockaddress(@indirectbr, %L2), i8* null], align 8
@@ -410,11 +410,11 @@
; CHECK-LABEL: name: trivial_bitcast_with_copy
; CHECK: [[A:%[0-9]+]]:_(p0) = COPY %x0
-; CHECK: G_BR %[[CAST:bb\.[0-9]+.cast]]
+; CHECK: G_BR %[[CAST:bb\.[0-9]+]]
-; CHECK: [[END:bb\.[0-9]+.end]]:
+; CHECK: [[END:bb\.[0-9]+]].{{[a-zA-Z0-9.]+}}:
-; CHECK: [[CAST]]:
+; CHECK: [[CAST]].{{[a-zA-Z0-9.]+}}:
; CHECK: {{%[0-9]+}}:_(p0) = COPY [[A]]
; CHECK: G_BR %[[END]]
define i64* @trivial_bitcast_with_copy(i8* %a) {
@@ -512,13 +512,13 @@
}
; CHECK-LABEL: name: test_phi
-; CHECK: G_BRCOND {{%.*}}, %[[TRUE:bb\.[0-9]+.true]]
-; CHECK: G_BR %[[FALSE:bb\.[0-9]+.false]]
+; CHECK: G_BRCOND {{%.*}}, %[[TRUE:bb\.[0-9]+]]
+; CHECK: G_BR %[[FALSE:bb\.[0-9]+]]
-; CHECK: [[TRUE]]:
+; CHECK: [[TRUE]].{{[a-zA-Z0-9.]+}}:
; CHECK: [[RES1:%[0-9]+]]:_(s32) = G_LOAD
-; CHECK: [[FALSE]]:
+; CHECK: [[FALSE]].{{[a-zA-Z0-9.]+}}:
; CHECK: [[RES2:%[0-9]+]]:_(s32) = G_LOAD
; CHECK: [[RES:%[0-9]+]]:_(s32) = G_PHI [[RES1]](s32), %[[TRUE]], [[RES2]](s32), %[[FALSE]]
@@ -554,7 +554,7 @@
; CHECK: [[IN:%[0-9]+]]:_(s32) = COPY %w0
; CHECK: [[ONE:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-; CHECK: {{bb.[0-9]+}}.next:
+; CHECK: bb.{{[0-9]+}}.{{[a-zA-Z0-9.]+}}:
; CHECK: [[SUM1:%[0-9]+]]:_(s32) = G_ADD [[IN]], [[ONE]]
; CHECK: [[SUM2:%[0-9]+]]:_(s32) = G_ADD [[IN]], [[ONE]]
; CHECK: [[RES:%[0-9]+]]:_(s32) = G_ADD [[SUM1]], [[SUM2]]
@@ -1226,7 +1226,7 @@
; CHECK: bb.{{[0-9]+}} (%ir-block.{{[0-9]+}}):
; CHECK: [[VAL_INT:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
; CHECK: [[VAL:%[0-9]+]]:_(p0) = G_INTTOPTR [[VAL_INT]](s32)
-; CHECK: {{bb.[0-9]+}}.next:
+; CHECK: bb.{{[0-9]+}}.{{[a-zA-Z0-9.]+}}:
br label %next
next:
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-exceptions.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-exceptions.ll
index 0e7fbd3..827fdd2 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-exceptions.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-exceptions.ll
@@ -9,7 +9,7 @@
; CHECK-LABEL: name: bar
; CHECK: body:
; CHECK-NEXT: bb.1 (%ir-block.0):
-; CHECK: successors: %[[GOOD:bb.[0-9]+.continue]]{{.*}}%[[BAD:bb.[0-9]+.broken]]
+; CHECK: successors: %[[GOOD:bb.[0-9]+]]{{.*}}%[[BAD:bb.[0-9]+]]
; CHECK: EH_LABEL
; CHECK: %w0 = COPY
; CHECK: BL @foo, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %w0, implicit-def %w0
@@ -17,7 +17,7 @@
; CHECK: EH_LABEL
; CHECK: G_BR %[[GOOD]]
-; CHECK: [[BAD]] (landing-pad):
+; CHECK: [[BAD]].{{[a-z]+}} (landing-pad):
; CHECK: EH_LABEL
; CHECK: [[UNDEF:%[0-9]+]]:_(s128) = G_IMPLICIT_DEF
; CHECK: [[PTR:%[0-9]+]]:_(p0) = COPY %x0
@@ -30,7 +30,7 @@
; CHECK: %x0 = COPY [[PTR_RET]]
; CHECK: %w1 = COPY [[SEL_RET]]
-; CHECK: [[GOOD]]:
+; CHECK: [[GOOD]].{{[a-z]+}}:
; CHECK: [[SEL:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: {{%[0-9]+}}:_(s128) = G_INSERT {{%[0-9]+}}, [[SEL]](s32), 64
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-exceptions.ll b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-exceptions.ll
index da40b27..01f955b 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-exceptions.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-exceptions.ll
@@ -10,9 +10,9 @@
; CHECK: name: bar
; CHECK: body:
; CHECK-NEXT: bb.1 (%ir-block.0):
-; CHECK: successors: %{{bb.[0-9]+.continue.*}}%[[LP:bb.[0-9]+.cleanup]]
+; CHECK: successors: %{{bb.[0-9]+.*}}%[[LP:bb.[0-9]+]]
-; CHECK: [[LP]] (landing-pad):
+; CHECK: [[LP]].{{[a-z]+}} (landing-pad):
; CHECK: EH_LABEL
; CHECK: [[PTR:%[0-9]+]]:_(p0) = COPY %x0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir
index 9c028eb..a732991 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir
@@ -43,16 +43,16 @@
- { id: 16, class: _ }
body: |
; CHECK-LABEL: name: test_simple
- ; CHECK: bb.0.entry:
- ; CHECK: successors: %bb.1.next(0x80000000)
+ ; CHECK: bb.0.{{[a-zA-Z0-9]+}}:
+ ; CHECK: successors: %bb.1(0x80000000)
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s64)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[COPY]](s64)
; CHECK: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[INTTOPTR]](p0)
; CHECK: %x0 = COPY [[PTRTOINT]](s64)
- ; CHECK: G_BRCOND [[TRUNC]](s1), %bb.1.next
- ; CHECK: bb.1.next:
+ ; CHECK: G_BRCOND [[TRUNC]](s1), %bb.1
+ ; CHECK: bb.1.{{[a-zA-Z0-9]+}}:
; CHECK: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[TRUNC2]], [[TRUNC3]]
@@ -95,7 +95,7 @@
%6(s64) = G_PTRTOINT %5
%x0 = COPY %6
- G_BRCOND %1, %bb.1.next
+ G_BRCOND %1, %bb.1
bb.1.next:
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/localizer-in-O0-pipeline.mir b/llvm/test/CodeGen/AArch64/GlobalISel/localizer-in-O0-pipeline.mir
index 997205b..d4ed70f 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/localizer-in-O0-pipeline.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/localizer-in-O0-pipeline.mir
@@ -59,19 +59,19 @@
# CHECK: %5:fpr(s32) = G_FCONSTANT float 2.000000e+00
# Second block will get the constant 1.0 when the localizer is enabled.
-# CHECK: bb.1.true:
+# CHECK: bb.1.{{[a-zA-Z0-9]+}}:
# OPT-NOT: G_FCONSTANT
# OPTNONE: [[FONE:%[0-9]+]]:fpr(s32) = G_FCONSTANT float 1.000000e+00
-# CHECK: G_BR %bb.3.end
+# CHECK: G_BR %bb.3
# Thrid block will get the constant 2.0 when the localizer is enabled.
-# CHECK: bb.2.false:
+# CHECK: bb.2.{{[a-zA-Z0-9]+}}:
# OPT-NOT: G_FCONSTANT
# OPTNONE: [[FTWO:%[0-9]+]]:fpr(s32) = G_FCONSTANT float 2.000000e+00
# CHECK: bb.3.end
-# OPTNONE: %2:fpr(s32) = PHI [[FONE]](s32), %bb.1.true, [[FTWO]](s32), %bb.2.false
-# OPT: %2:fpr(s32) = PHI %4(s32), %bb.1.true, %5(s32), %bb.2.false
+# OPTNONE: %2:fpr(s32) = PHI [[FONE]](s32), %bb.1, [[FTWO]](s32), %bb.2
+# OPT: %2:fpr(s32) = PHI %4(s32), %bb.1, %5(s32), %bb.2
# CHECK-NEXT: G_FADD %0, %2
body: |
bb.0 (%ir-block.0):
@@ -82,16 +82,16 @@
%1(s1) = G_TRUNC %6
%4(s32) = G_FCONSTANT float 1.000000e+00
%5(s32) = G_FCONSTANT float 2.000000e+00
- G_BRCOND %1(s1), %bb.1.true
- G_BR %bb.2.false
+ G_BRCOND %1(s1), %bb.1
+ G_BR %bb.2
bb.1.true:
- G_BR %bb.3.end
+ G_BR %bb.3
bb.2.false:
bb.3.end:
- %2(s32) = PHI %4(s32), %bb.1.true, %5(s32), %bb.2.false
+ %2(s32) = PHI %4(s32), %bb.1, %5(s32), %bb.2
%3(s32) = G_FADD %0, %2
%s0 = COPY %3(s32)
RET_ReallyLR implicit %s0
diff --git a/llvm/test/CodeGen/AArch64/aarch64-fix-cortex-a53-835769.ll b/llvm/test/CodeGen/AArch64/aarch64-fix-cortex-a53-835769.ll
index 51c32b4..eafb412 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-fix-cortex-a53-835769.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-fix-cortex-a53-835769.ll
@@ -508,12 +508,12 @@
; CHECK: ldr
; CHECK-NEXT: nop
; CHECK-NEXT: .Ltmp
-; CHECK-NEXT: BB
+; CHECK-NEXT: %bb.
; CHECK-NEXT: madd
; CHECK-NOWORKAROUND-LABEL: fall_through
; CHECK-NOWORKAROUND: ldr
; CHECK-NOWORKAROUND-NEXT: .Ltmp
-; CHECK-NOWORKAROUND-NEXT: BB
+; CHECK-NOWORKAROUND-NEXT: %bb.
; CHECK-NOWORKAROUND-NEXT: madd
; No checks for this, just check it doesn't crash
diff --git a/llvm/test/CodeGen/AArch64/aarch64-stp-cluster.ll b/llvm/test/CodeGen/AArch64/aarch64-stp-cluster.ll
index 0ee32f7..c6bdbe4 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-stp-cluster.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-stp-cluster.ll
@@ -2,7 +2,7 @@
; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a57 -verify-misched -debug-only=machine-scheduler -aarch64-enable-stp-suppress=false -o - 2>&1 > /dev/null | FileCheck %s
; CHECK: ********** MI Scheduling **********
-; CHECK-LABEL: stp_i64_scale:BB#0
+; CHECK-LABEL: stp_i64_scale:%bb.0
; CHECK:Cluster ld/st SU(4) - SU(3)
; CHECK:Cluster ld/st SU(2) - SU(5)
; CHECK:SU(4): STRXui %1, %0, 1
@@ -23,7 +23,7 @@
}
; CHECK: ********** MI Scheduling **********
-; CHECK-LABEL: stp_i32_scale:BB#0
+; CHECK-LABEL: stp_i32_scale:%bb.0
; CHECK:Cluster ld/st SU(4) - SU(3)
; CHECK:Cluster ld/st SU(2) - SU(5)
; CHECK:SU(4): STRWui %1, %0, 1
@@ -44,7 +44,7 @@
}
; CHECK:********** MI Scheduling **********
-; CHECK-LABEL:stp_i64_unscale:BB#0 entry
+; CHECK-LABEL:stp_i64_unscale:%bb.0 entry
; CHECK:Cluster ld/st SU(5) - SU(2)
; CHECK:Cluster ld/st SU(4) - SU(3)
; CHECK:SU(5): STURXi %1, %0, -32
@@ -65,7 +65,7 @@
}
; CHECK:********** MI Scheduling **********
-; CHECK-LABEL:stp_i32_unscale:BB#0 entry
+; CHECK-LABEL:stp_i32_unscale:%bb.0 entry
; CHECK:Cluster ld/st SU(5) - SU(2)
; CHECK:Cluster ld/st SU(4) - SU(3)
; CHECK:SU(5): STURWi %1, %0, -16
@@ -86,7 +86,7 @@
}
; CHECK:********** MI Scheduling **********
-; CHECK-LABEL:stp_double:BB#0
+; CHECK-LABEL:stp_double:%bb.0
; CHECK:Cluster ld/st SU(3) - SU(4)
; CHECK:Cluster ld/st SU(2) - SU(5)
; CHECK:SU(3): STRDui %1, %0, 1
@@ -107,7 +107,7 @@
}
; CHECK:********** MI Scheduling **********
-; CHECK-LABEL:stp_float:BB#0
+; CHECK-LABEL:stp_float:%bb.0
; CHECK:Cluster ld/st SU(3) - SU(4)
; CHECK:Cluster ld/st SU(2) - SU(5)
; CHECK:SU(3): STRSui %1, %0, 1
@@ -128,7 +128,7 @@
}
; CHECK: ********** MI Scheduling **********
-; CHECK-LABEL: stp_volatile:BB#0
+; CHECK-LABEL: stp_volatile:%bb.0
; CHECK-NOT: Cluster ld/st
; CHECK:SU(2): STRXui %1, %0, 3; mem:Volatile
; CHECK:SU(3): STRXui %1, %0, 2; mem:Volatile
diff --git a/llvm/test/CodeGen/AArch64/analyze-branch.ll b/llvm/test/CodeGen/AArch64/analyze-branch.ll
index 932cd75..4f902ef 100644
--- a/llvm/test/CodeGen/AArch64/analyze-branch.ll
+++ b/llvm/test/CodeGen/AArch64/analyze-branch.ll
@@ -18,7 +18,7 @@
; CHECK: cmp {{w[0-9]+}}, #42
; CHECK: b.ne [[FALSE:.LBB[0-9]+_[0-9]+]]
-; CHECK-NEXT: // BB#
+; CHECK-NEXT: // %bb.
; CHECK-NEXT: bl test_true
; CHECK: [[FALSE]]:
@@ -41,7 +41,7 @@
; CHECK: cmp {{w[0-9]+}}, #42
; CHECK: b.eq [[TRUE:.LBB[0-9]+_[0-9]+]]
-; CHECK-NEXT: // BB#
+; CHECK-NEXT: // %bb.
; CHECK-NEXT: bl test_false
; CHECK: [[TRUE]]:
@@ -62,7 +62,7 @@
br i1 %tst, label %true, label %false, !prof !0
; CHECK: cbnz {{w[0-9]+}}, [[FALSE:.LBB[0-9]+_[0-9]+]]
-; CHECK-NEXT: // BB#
+; CHECK-NEXT: // %bb.
; CHECK-NEXT: bl test_true
; CHECK: [[FALSE]]:
@@ -83,7 +83,7 @@
br i1 %tst, label %true, label %false, !prof !1
; CHECK: cbz {{x[0-9]+}}, [[TRUE:.LBB[0-9]+_[0-9]+]]
-; CHECK-NEXT: // BB#
+; CHECK-NEXT: // %bb.
; CHECK-NEXT: bl test_false
; CHECK: [[TRUE]]:
@@ -104,7 +104,7 @@
br i1 %tst, label %true, label %false, !prof !0
; CHECK: cbz {{w[0-9]+}}, [[FALSE:.LBB[0-9]+_[0-9]+]]
-; CHECK-NEXT: // BB#
+; CHECK-NEXT: // %bb.
; CHECK-NEXT: bl test_true
; CHECK: [[FALSE]]:
@@ -125,7 +125,7 @@
br i1 %tst, label %true, label %false, !prof !1
; CHECK: cbnz {{x[0-9]+}}, [[TRUE:.LBB[0-9]+_[0-9]+]]
-; CHECK-NEXT: // BB#
+; CHECK-NEXT: // %bb.
; CHECK-NEXT: bl test_false
; CHECK: [[TRUE]]:
@@ -147,7 +147,7 @@
br i1 %tst, label %true, label %false, !prof !0
; CHECK: tbnz {{w[0-9]+}}, #15, [[FALSE:.LBB[0-9]+_[0-9]+]]
-; CHECK-NEXT: // BB#
+; CHECK-NEXT: // %bb.
; CHECK-NEXT: bl test_true
; CHECK: [[FALSE]]:
@@ -169,7 +169,7 @@
br i1 %tst, label %true, label %false, !prof !1
; CHECK: tbz {{[wx][0-9]+}}, #15, [[TRUE:.LBB[0-9]+_[0-9]+]]
-; CHECK-NEXT: // BB#
+; CHECK-NEXT: // %bb.
; CHECK-NEXT: bl test_false
; CHECK: [[TRUE]]:
@@ -192,7 +192,7 @@
br i1 %tst, label %true, label %false, !prof !0
; CHECK: tbz {{w[0-9]+}}, #15, [[FALSE:.LBB[0-9]+_[0-9]+]]
-; CHECK-NEXT: // BB#
+; CHECK-NEXT: // %bb.
; CHECK-NEXT: bl test_true
; CHECK: [[FALSE]]:
@@ -214,7 +214,7 @@
br i1 %tst, label %true, label %false, !prof !1
; CHECK: tbnz {{[wx][0-9]+}}, #15, [[TRUE:.LBB[0-9]+_[0-9]+]]
-; CHECK-NEXT: // BB#
+; CHECK-NEXT: // %bb.
; CHECK-NEXT: bl test_false
; CHECK: [[TRUE]]:
diff --git a/llvm/test/CodeGen/AArch64/arm64-ccmp.ll b/llvm/test/CodeGen/AArch64/arm64-ccmp.ll
index a910585..b18e638 100644
--- a/llvm/test/CodeGen/AArch64/arm64-ccmp.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-ccmp.ll
@@ -132,6 +132,7 @@
; Floating point compare.
; CHECK: single_fcmp
+; CHECK: ; %bb.
; CHECK: cmp
; CHECK-NOT: b.
; CHECK: fccmp {{.*}}, #8, ge
@@ -448,7 +449,7 @@
; Test the IR CCs that expand to two cond codes.
; CHECK-LABEL: select_and_olt_one:
-; CHECK-LABEL: ; BB#0:
+; CHECK-LABEL: ; %bb.0:
; CHECK-NEXT: fcmp d0, d1
; CHECK-NEXT: fccmp d2, d3, #4, mi
; CHECK-NEXT: fccmp d2, d3, #1, ne
@@ -463,7 +464,7 @@
}
; CHECK-LABEL: select_and_one_olt:
-; CHECK-LABEL: ; BB#0:
+; CHECK-LABEL: ; %bb.0:
; CHECK-NEXT: fcmp d0, d1
; CHECK-NEXT: fccmp d0, d1, #1, ne
; CHECK-NEXT: fccmp d2, d3, #0, vc
@@ -478,7 +479,7 @@
}
; CHECK-LABEL: select_and_olt_ueq:
-; CHECK-LABEL: ; BB#0:
+; CHECK-LABEL: ; %bb.0:
; CHECK-NEXT: fcmp d0, d1
; CHECK-NEXT: fccmp d2, d3, #0, mi
; CHECK-NEXT: fccmp d2, d3, #8, le
@@ -493,7 +494,7 @@
}
; CHECK-LABEL: select_and_ueq_olt:
-; CHECK-LABEL: ; BB#0:
+; CHECK-LABEL: ; %bb.0:
; CHECK-NEXT: fcmp d0, d1
; CHECK-NEXT: fccmp d0, d1, #8, le
; CHECK-NEXT: fccmp d2, d3, #0, pl
@@ -508,7 +509,7 @@
}
; CHECK-LABEL: select_or_olt_one:
-; CHECK-LABEL: ; BB#0:
+; CHECK-LABEL: ; %bb.0:
; CHECK-NEXT: fcmp d0, d1
; CHECK-NEXT: fccmp d2, d3, #0, pl
; CHECK-NEXT: fccmp d2, d3, #8, le
@@ -523,7 +524,7 @@
}
; CHECK-LABEL: select_or_one_olt:
-; CHECK-LABEL: ; BB#0:
+; CHECK-LABEL: ; %bb.0:
; CHECK-NEXT: fcmp d0, d1
; CHECK-NEXT: fccmp d0, d1, #1, ne
; CHECK-NEXT: fccmp d2, d3, #8, vs
@@ -538,7 +539,7 @@
}
; CHECK-LABEL: select_or_olt_ueq:
-; CHECK-LABEL: ; BB#0:
+; CHECK-LABEL: ; %bb.0:
; CHECK-NEXT: fcmp d0, d1
; CHECK-NEXT: fccmp d2, d3, #4, pl
; CHECK-NEXT: fccmp d2, d3, #1, ne
@@ -553,7 +554,7 @@
}
; CHECK-LABEL: select_or_ueq_olt:
-; CHECK-LABEL: ; BB#0:
+; CHECK-LABEL: ; %bb.0:
; CHECK-NEXT: fcmp d0, d1
; CHECK-NEXT: fccmp d0, d1, #8, le
; CHECK-NEXT: fccmp d2, d3, #8, mi
@@ -568,7 +569,7 @@
}
; CHECK-LABEL: select_or_olt_ogt_ueq:
-; CHECK-LABEL: ; BB#0:
+; CHECK-LABEL: ; %bb.0:
; CHECK-NEXT: fcmp d0, d1
; CHECK-NEXT: fccmp d2, d3, #0, pl
; CHECK-NEXT: fccmp d4, d5, #4, le
@@ -586,7 +587,7 @@
}
; CHECK-LABEL: select_or_olt_ueq_ogt:
-; CHECK-LABEL: ; BB#0:
+; CHECK-LABEL: ; %bb.0:
; CHECK-NEXT: fcmp d0, d1
; CHECK-NEXT: fccmp d2, d3, #4, pl
; CHECK-NEXT: fccmp d2, d3, #1, ne
@@ -606,7 +607,7 @@
; Verify that we correctly promote f16.
; CHECK-LABEL: half_select_and_olt_oge:
-; CHECK-LABEL: ; BB#0:
+; CHECK-LABEL: ; %bb.0:
; CHECK-DAG: fcvt [[S0:s[0-9]+]], h0
; CHECK-DAG: fcvt [[S1:s[0-9]+]], h1
; CHECK-NEXT: fcmp [[S0]], [[S1]]
@@ -624,7 +625,7 @@
}
; CHECK-LABEL: half_select_and_olt_one:
-; CHECK-LABEL: ; BB#0:
+; CHECK-LABEL: ; %bb.0:
; CHECK-DAG: fcvt [[S0:s[0-9]+]], h0
; CHECK-DAG: fcvt [[S1:s[0-9]+]], h1
; CHECK-NEXT: fcmp [[S0]], [[S1]]
diff --git a/llvm/test/CodeGen/AArch64/arm64-fp128.ll b/llvm/test/CodeGen/AArch64/arm64-fp128.ll
index 2ae0da2..3561d8f 100644
--- a/llvm/test/CodeGen/AArch64/arm64-fp128.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-fp128.ll
@@ -195,7 +195,7 @@
iftrue:
ret i32 42
-; CHECK-NEXT: BB#
+; CHECK-NEXT: %bb.
; CHECK-NEXT: mov w0, #42
; CHECK: ret
iffalse:
@@ -211,7 +211,7 @@
store fp128 %val, fp128* @lhs, align 16
; CHECK: tst w0, #0x1
; CHECK-NEXT: b.eq [[IFFALSE:.LBB[0-9]+_[0-9]+]]
-; CHECK-NEXT: BB#
+; CHECK-NEXT: %bb.
; CHECK-NEXT: mov v[[VAL:[0-9]+]].16b, v0.16b
; CHECK-NEXT: [[IFFALSE]]:
; CHECK: str q[[VAL]], [{{x[0-9]+}}, :lo12:lhs]
diff --git a/llvm/test/CodeGen/AArch64/arm64-icmp-opt.ll b/llvm/test/CodeGen/AArch64/arm64-icmp-opt.ll
index 12eae0e..1ed5c5e 100644
--- a/llvm/test/CodeGen/AArch64/arm64-icmp-opt.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-icmp-opt.ll
@@ -7,7 +7,7 @@
define i32 @t1(i64 %a) {
; CHECK-LABEL: t1:
-; CHECK: // BB#0:
+; CHECK: // %bb.0:
; CHECK-NEXT: lsr x8, x0, #63
; CHECK-NEXT: eor w0, w8, #0x1
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll b/llvm/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll
index cdbadfe..b63e739 100644
--- a/llvm/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll
@@ -6176,7 +6176,7 @@
; Check for dependencies between the vector and the scalar load.
define <4 x float> @test_v4f32_post_reg_ld1lane_dep_vec_on_load(float* %bar, float** %ptr, i64 %inc, <4 x float>* %dep_ptr_1, <4 x float>* %dep_ptr_2, <4 x float> %vec) {
; CHECK-LABEL: test_v4f32_post_reg_ld1lane_dep_vec_on_load:
-; CHECK: BB#0:
+; CHECK: %bb.0:
; CHECK-NEXT: ldr s[[LD:[0-9]+]], [x0]
; CHECK-NEXT: str q0, [x3]
; CHECK-NEXT: ldr q0, [x4]
diff --git a/llvm/test/CodeGen/AArch64/arm64-ldp-cluster.ll b/llvm/test/CodeGen/AArch64/arm64-ldp-cluster.ll
index ca50e11..370db23 100644
--- a/llvm/test/CodeGen/AArch64/arm64-ldp-cluster.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-ldp-cluster.ll
@@ -4,12 +4,12 @@
; Test ldr clustering.
; CHECK: ********** MI Scheduling **********
-; CHECK-LABEL: ldr_int:BB#0
+; CHECK-LABEL: ldr_int:%bb.0
; CHECK: Cluster ld/st SU(1) - SU(2)
; CHECK: SU(1): %{{[0-9]+}}<def> = LDRWui
; CHECK: SU(2): %{{[0-9]+}}<def> = LDRWui
; EXYNOS: ********** MI Scheduling **********
-; EXYNOS-LABEL: ldr_int:BB#0
+; EXYNOS-LABEL: ldr_int:%bb.0
; EXYNOS: Cluster ld/st SU(1) - SU(2)
; EXYNOS: SU(1): %{{[0-9]+}}<def> = LDRWui
; EXYNOS: SU(2): %{{[0-9]+}}<def> = LDRWui
@@ -24,12 +24,12 @@
; Test ldpsw clustering
; CHECK: ********** MI Scheduling **********
-; CHECK-LABEL: ldp_sext_int:BB#0
+; CHECK-LABEL: ldp_sext_int:%bb.0
; CHECK: Cluster ld/st SU(1) - SU(2)
; CHECK: SU(1): %{{[0-9]+}}<def> = LDRSWui
; CHECK: SU(2): %{{[0-9]+}}<def> = LDRSWui
; EXYNOS: ********** MI Scheduling **********
-; EXYNOS-LABEL: ldp_sext_int:BB#0
+; EXYNOS-LABEL: ldp_sext_int:%bb.0
; EXYNOS: Cluster ld/st SU(1) - SU(2)
; EXYNOS: SU(1): %{{[0-9]+}}<def> = LDRSWui
; EXYNOS: SU(2): %{{[0-9]+}}<def> = LDRSWui
@@ -45,12 +45,12 @@
; Test ldur clustering.
; CHECK: ********** MI Scheduling **********
-; CHECK-LABEL: ldur_int:BB#0
+; CHECK-LABEL: ldur_int:%bb.0
; CHECK: Cluster ld/st SU(2) - SU(1)
; CHECK: SU(1): %{{[0-9]+}}<def> = LDURWi
; CHECK: SU(2): %{{[0-9]+}}<def> = LDURWi
; EXYNOS: ********** MI Scheduling **********
-; EXYNOS-LABEL: ldur_int:BB#0
+; EXYNOS-LABEL: ldur_int:%bb.0
; EXYNOS: Cluster ld/st SU(2) - SU(1)
; EXYNOS: SU(1): %{{[0-9]+}}<def> = LDURWi
; EXYNOS: SU(2): %{{[0-9]+}}<def> = LDURWi
@@ -65,12 +65,12 @@
; Test sext + zext clustering.
; CHECK: ********** MI Scheduling **********
-; CHECK-LABEL: ldp_half_sext_zext_int:BB#0
+; CHECK-LABEL: ldp_half_sext_zext_int:%bb.0
; CHECK: Cluster ld/st SU(3) - SU(4)
; CHECK: SU(3): %{{[0-9]+}}<def> = LDRSWui
; CHECK: SU(4): %{{[0-9]+}}:sub_32<def,read-undef> = LDRWui
; EXYNOS: ********** MI Scheduling **********
-; EXYNOS-LABEL: ldp_half_sext_zext_int:BB#0
+; EXYNOS-LABEL: ldp_half_sext_zext_int:%bb.0
; EXYNOS: Cluster ld/st SU(3) - SU(4)
; EXYNOS: SU(3): %{{[0-9]+}}<def> = LDRSWui
; EXYNOS: SU(4): %{{[0-9]+}}:sub_32<def,read-undef> = LDRWui
@@ -88,12 +88,12 @@
; Test zext + sext clustering.
; CHECK: ********** MI Scheduling **********
-; CHECK-LABEL: ldp_half_zext_sext_int:BB#0
+; CHECK-LABEL: ldp_half_zext_sext_int:%bb.0
; CHECK: Cluster ld/st SU(3) - SU(4)
; CHECK: SU(3): %{{[0-9]+}}:sub_32<def,read-undef> = LDRWui
; CHECK: SU(4): %{{[0-9]+}}<def> = LDRSWui
; EXYNOS: ********** MI Scheduling **********
-; EXYNOS-LABEL: ldp_half_zext_sext_int:BB#0
+; EXYNOS-LABEL: ldp_half_zext_sext_int:%bb.0
; EXYNOS: Cluster ld/st SU(3) - SU(4)
; EXYNOS: SU(3): %{{[0-9]+}}:sub_32<def,read-undef> = LDRWui
; EXYNOS: SU(4): %{{[0-9]+}}<def> = LDRSWui
@@ -111,12 +111,12 @@
; Verify we don't cluster volatile loads.
; CHECK: ********** MI Scheduling **********
-; CHECK-LABEL: ldr_int_volatile:BB#0
+; CHECK-LABEL: ldr_int_volatile:%bb.0
; CHECK-NOT: Cluster ld/st
; CHECK: SU(1): %{{[0-9]+}}<def> = LDRWui
; CHECK: SU(2): %{{[0-9]+}}<def> = LDRWui
; EXYNOS: ********** MI Scheduling **********
-; EXYNOS-LABEL: ldr_int_volatile:BB#0
+; EXYNOS-LABEL: ldr_int_volatile:%bb.0
; EXYNOS-NOT: Cluster ld/st
; EXYNOS: SU(1): %{{[0-9]+}}<def> = LDRWui
; EXYNOS: SU(2): %{{[0-9]+}}<def> = LDRWui
@@ -131,12 +131,12 @@
; Test ldq clustering (no clustering for Exynos).
; CHECK: ********** MI Scheduling **********
-; CHECK-LABEL: ldq_cluster:BB#0
+; CHECK-LABEL: ldq_cluster:%bb.0
; CHECK: Cluster ld/st SU(1) - SU(3)
; CHECK: SU(1): %{{[0-9]+}}<def> = LDRQui
; CHECK: SU(3): %{{[0-9]+}}<def> = LDRQui
; EXYNOS: ********** MI Scheduling **********
-; EXYNOS-LABEL: ldq_cluster:BB#0
+; EXYNOS-LABEL: ldq_cluster:%bb.0
; EXYNOS-NOT: Cluster ld/st
define <2 x i64> @ldq_cluster(i64* %p) {
%a1 = bitcast i64* %p to <2 x i64>*
diff --git a/llvm/test/CodeGen/AArch64/arm64-misched-basic-A53.ll b/llvm/test/CodeGen/AArch64/arm64-misched-basic-A53.ll
index 307d1ec..07df9cb 100644
--- a/llvm/test/CodeGen/AArch64/arm64-misched-basic-A53.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-misched-basic-A53.ll
@@ -8,7 +8,7 @@
;
; CHECK: ********** MI Scheduling **********
; CHECK: main
-; CHECK: *** Final schedule for BB#2 ***
+; CHECK: *** Final schedule for %bb.2 ***
; CHECK: MADDWrrr
; CHECK: ADDWri
; CHECK: ********** INTERVALS **********
@@ -83,8 +83,8 @@
; after it, this test checks to make sure there are more than one.
;
; CHECK: ********** MI Scheduling **********
-; CHECK: neon4xfloat:BB#0
-; CHECK: *** Final schedule for BB#0 ***
+; CHECK: neon4xfloat:%bb.0
+; CHECK: *** Final schedule for %bb.0 ***
; CHECK: FDIVv4f32
; CHECK: FADDv4f32
; CHECK: FADDv4f32
@@ -130,7 +130,7 @@
; are otherwise ready are jammed in the pending queue.
; CHECK: ********** MI Scheduling **********
; CHECK: testResourceConflict
-; CHECK: *** Final schedule for BB#0 ***
+; CHECK: *** Final schedule for %bb.0 ***
; CHECK: BRK
; CHECK: ********** INTERVALS **********
define void @testResourceConflict(float* %ptr) {
@@ -178,7 +178,7 @@
; Resource contention on LDST.
; CHECK: ********** MI Scheduling **********
; CHECK: testLdStConflict
-; CHECK: *** Final schedule for BB#1 ***
+; CHECK: *** Final schedule for %bb.1 ***
; CHECK: LD4Fourv2d
; CHECK: STRQui
; CHECK: ********** INTERVALS **********
diff --git a/llvm/test/CodeGen/AArch64/arm64-misched-basic-A57.ll b/llvm/test/CodeGen/AArch64/arm64-misched-basic-A57.ll
index 82ba18c..711d2f7 100644
--- a/llvm/test/CodeGen/AArch64/arm64-misched-basic-A57.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-misched-basic-A57.ll
@@ -8,10 +8,10 @@
;
; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a57 -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
; CHECK: ********** MI Scheduling **********
-; CHECK: main:BB#2
+; CHECK: main:%bb.2
; CHECK: LDR
; CHECK: Latency : 4
-; CHECK: *** Final schedule for BB#2 ***
+; CHECK: *** Final schedule for %bb.2 ***
; CHECK: LDR
; CHECK: LDR
; CHECK-NOT: LDR
diff --git a/llvm/test/CodeGen/AArch64/arm64-misched-memdep-bug.ll b/llvm/test/CodeGen/AArch64/arm64-misched-memdep-bug.ll
index b2bfc13..8c81cf4 100644
--- a/llvm/test/CodeGen/AArch64/arm64-misched-memdep-bug.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-misched-memdep-bug.ll
@@ -4,7 +4,7 @@
; Test for bug in misched memory dependency calculation.
;
; CHECK: ********** MI Scheduling **********
-; CHECK: misched_bug:BB#0 entry
+; CHECK: misched_bug:%bb.0 entry
; CHECK: SU(2): %2<def> = LDRWui %0, 1; mem:LD4[%ptr1_plus1] GPR32:%2 GPR64common:%0
; CHECK: Successors:
; CHECK-NEXT: SU(5): Data Latency=4 Reg=%2
diff --git a/llvm/test/CodeGen/AArch64/arm64-variadic-aapcs.ll b/llvm/test/CodeGen/AArch64/arm64-variadic-aapcs.ll
index 375877c..c6c7a65 100644
--- a/llvm/test/CodeGen/AArch64/arm64-variadic-aapcs.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-variadic-aapcs.ll
@@ -113,7 +113,7 @@
define void @test_va_end() nounwind {
; CHECK-LABEL: test_va_end:
-; CHECK-NEXT: BB#0
+; CHECK-NEXT: %bb.0
%addr = bitcast %va_list* @var to i8*
call void @llvm.va_end(i8* %addr)
diff --git a/llvm/test/CodeGen/AArch64/bics.ll b/llvm/test/CodeGen/AArch64/bics.ll
index 53aa28a..244aacb 100644
--- a/llvm/test/CodeGen/AArch64/bics.ll
+++ b/llvm/test/CodeGen/AArch64/bics.ll
@@ -2,7 +2,7 @@
define i1 @andn_cmp(i32 %x, i32 %y) {
; CHECK-LABEL: andn_cmp:
-; CHECK: // BB#0:
+; CHECK: // %bb.0:
; CHECK-NEXT: bics wzr, w1, w0
; CHECK-NEXT: cset w0, eq
; CHECK-NEXT: ret
@@ -15,7 +15,7 @@
define i1 @and_cmp(i32 %x, i32 %y) {
; CHECK-LABEL: and_cmp:
-; CHECK: // BB#0:
+; CHECK: // %bb.0:
; CHECK-NEXT: bics wzr, w1, w0
; CHECK-NEXT: cset w0, eq
; CHECK-NEXT: ret
@@ -27,7 +27,7 @@
define i1 @and_cmp_const(i32 %x) {
; CHECK-LABEL: and_cmp_const:
-; CHECK: // BB#0:
+; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #43
; CHECK-NEXT: bics wzr, w8, w0
; CHECK-NEXT: cset w0, eq
diff --git a/llvm/test/CodeGen/AArch64/branch-relax-cbz.ll b/llvm/test/CodeGen/AArch64/branch-relax-cbz.ll
index d13c0f6..cddecbd9 100644
--- a/llvm/test/CodeGen/AArch64/branch-relax-cbz.ll
+++ b/llvm/test/CodeGen/AArch64/branch-relax-cbz.ll
@@ -4,7 +4,7 @@
; CHECK: cmn x{{[0-9]+}}, #5
; CHECK-NEXT: b.le [[B2:LBB[0-9]+_[0-9]+]]
-; CHECK-NEXT: ; BB#1: ; %b3
+; CHECK-NEXT: ; %bb.1: ; %b3
; CHECK: ldr [[LOAD:w[0-9]+]]
; CHECK: cbnz [[LOAD]], [[B8:LBB[0-9]+_[0-9]+]]
; CHECK-NEXT: b [[B7:LBB[0-9]+_[0-9]+]]
diff --git a/llvm/test/CodeGen/AArch64/fast-isel-assume.ll b/llvm/test/CodeGen/AArch64/fast-isel-assume.ll
index d39a907..50f510a 100644
--- a/llvm/test/CodeGen/AArch64/fast-isel-assume.ll
+++ b/llvm/test/CodeGen/AArch64/fast-isel-assume.ll
@@ -3,7 +3,7 @@
; Check that we ignore the assume intrinsic.
; CHECK-LABEL: test:
-; CHECK: // BB#0:
+; CHECK: // %bb.0:
; CHECK-NEXT: ret
define void @test(i32 %a) {
%tmp0 = icmp slt i32 %a, 0
diff --git a/llvm/test/CodeGen/AArch64/fast-isel-atomic.ll b/llvm/test/CodeGen/AArch64/fast-isel-atomic.ll
index 195b8be..ec61261 100644
--- a/llvm/test/CodeGen/AArch64/fast-isel-atomic.ll
+++ b/llvm/test/CodeGen/AArch64/fast-isel-atomic.ll
@@ -5,7 +5,7 @@
; currently match, so we might as well check both! Feel free to remove SDAG.
; CHECK-LABEL: atomic_store_monotonic_8:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: strb w1, [x0]
; CHECK-NEXT: ret
define void @atomic_store_monotonic_8(i8* %p, i8 %val) #0 {
@@ -14,7 +14,7 @@
}
; CHECK-LABEL: atomic_store_monotonic_8_off:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: strb w1, [x0, #1]
; CHECK-NEXT: ret
define void @atomic_store_monotonic_8_off(i8* %p, i8 %val) #0 {
@@ -24,7 +24,7 @@
}
; CHECK-LABEL: atomic_store_monotonic_16:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: strh w1, [x0]
; CHECK-NEXT: ret
define void @atomic_store_monotonic_16(i16* %p, i16 %val) #0 {
@@ -33,7 +33,7 @@
}
; CHECK-LABEL: atomic_store_monotonic_16_off:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: strh w1, [x0, #2]
; CHECK-NEXT: ret
define void @atomic_store_monotonic_16_off(i16* %p, i16 %val) #0 {
@@ -43,7 +43,7 @@
}
; CHECK-LABEL: atomic_store_monotonic_32:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: str w1, [x0]
; CHECK-NEXT: ret
define void @atomic_store_monotonic_32(i32* %p, i32 %val) #0 {
@@ -52,7 +52,7 @@
}
; CHECK-LABEL: atomic_store_monotonic_32_off:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: str w1, [x0, #4]
; CHECK-NEXT: ret
define void @atomic_store_monotonic_32_off(i32* %p, i32 %val) #0 {
@@ -62,7 +62,7 @@
}
; CHECK-LABEL: atomic_store_monotonic_64:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: str x1, [x0]
; CHECK-NEXT: ret
define void @atomic_store_monotonic_64(i64* %p, i64 %val) #0 {
@@ -71,7 +71,7 @@
}
; CHECK-LABEL: atomic_store_monotonic_64_off:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: str x1, [x0, #8]
; CHECK-NEXT: ret
define void @atomic_store_monotonic_64_off(i64* %p, i64 %val) #0 {
@@ -81,7 +81,7 @@
}
; CHECK-LABEL: atomic_store_release_8:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: stlrb w1, [x0]
; CHECK-NEXT: ret
define void @atomic_store_release_8(i8* %p, i8 %val) #0 {
@@ -90,7 +90,7 @@
}
; CHECK-LABEL: atomic_store_release_8_off:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: add x0, x0, #1
; CHECK-NEXT: stlrb w1, [x0]
; CHECK-NEXT: ret
@@ -101,7 +101,7 @@
}
; CHECK-LABEL: atomic_store_release_16:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: stlrh w1, [x0]
; CHECK-NEXT: ret
define void @atomic_store_release_16(i16* %p, i16 %val) #0 {
@@ -110,7 +110,7 @@
}
; CHECK-LABEL: atomic_store_release_16_off:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: add x0, x0, #2
; CHECK-NEXT: stlrh w1, [x0]
; CHECK-NEXT: ret
@@ -121,7 +121,7 @@
}
; CHECK-LABEL: atomic_store_release_32:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: stlr w1, [x0]
; CHECK-NEXT: ret
define void @atomic_store_release_32(i32* %p, i32 %val) #0 {
@@ -130,7 +130,7 @@
}
; CHECK-LABEL: atomic_store_release_32_off:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: add x0, x0, #4
; CHECK-NEXT: stlr w1, [x0]
; CHECK-NEXT: ret
@@ -141,7 +141,7 @@
}
; CHECK-LABEL: atomic_store_release_64:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: stlr x1, [x0]
; CHECK-NEXT: ret
define void @atomic_store_release_64(i64* %p, i64 %val) #0 {
@@ -150,7 +150,7 @@
}
; CHECK-LABEL: atomic_store_release_64_off:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: add x0, x0, #8
; CHECK-NEXT: stlr x1, [x0]
; CHECK-NEXT: ret
@@ -162,7 +162,7 @@
; CHECK-LABEL: atomic_store_seq_cst_8:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: stlrb w1, [x0]
; CHECK-NEXT: ret
define void @atomic_store_seq_cst_8(i8* %p, i8 %val) #0 {
@@ -171,7 +171,7 @@
}
; CHECK-LABEL: atomic_store_seq_cst_8_off:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: add x0, x0, #1
; CHECK-NEXT: stlrb w1, [x0]
; CHECK-NEXT: ret
@@ -182,7 +182,7 @@
}
; CHECK-LABEL: atomic_store_seq_cst_16:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: stlrh w1, [x0]
; CHECK-NEXT: ret
define void @atomic_store_seq_cst_16(i16* %p, i16 %val) #0 {
@@ -191,7 +191,7 @@
}
; CHECK-LABEL: atomic_store_seq_cst_16_off:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: add x0, x0, #2
; CHECK-NEXT: stlrh w1, [x0]
; CHECK-NEXT: ret
@@ -202,7 +202,7 @@
}
; CHECK-LABEL: atomic_store_seq_cst_32:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: stlr w1, [x0]
; CHECK-NEXT: ret
define void @atomic_store_seq_cst_32(i32* %p, i32 %val) #0 {
@@ -211,7 +211,7 @@
}
; CHECK-LABEL: atomic_store_seq_cst_32_off:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: add x0, x0, #4
; CHECK-NEXT: stlr w1, [x0]
; CHECK-NEXT: ret
@@ -222,7 +222,7 @@
}
; CHECK-LABEL: atomic_store_seq_cst_64:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: stlr x1, [x0]
; CHECK-NEXT: ret
define void @atomic_store_seq_cst_64(i64* %p, i64 %val) #0 {
@@ -231,7 +231,7 @@
}
; CHECK-LABEL: atomic_store_seq_cst_64_off:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: add x0, x0, #8
; CHECK-NEXT: stlr x1, [x0]
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/AArch64/fast-isel-cmp-vec.ll b/llvm/test/CodeGen/AArch64/fast-isel-cmp-vec.ll
index 89b368f..d5b64c5 100644
--- a/llvm/test/CodeGen/AArch64/fast-isel-cmp-vec.ll
+++ b/llvm/test/CodeGen/AArch64/fast-isel-cmp-vec.ll
@@ -8,9 +8,9 @@
define <2 x i32> @icmp_v2i32(<2 x i32> %a) {
; CHECK-LABEL: icmp_v2i32:
-; CHECK: ; BB#0:
+; CHECK: ; %bb.0:
; CHECK-NEXT: cmeq.2s [[CMP:v[0-9]+]], v0, #0
-; CHECK-NEXT: ; BB#1:
+; CHECK-NEXT: ; %bb.1:
; CHECK-NEXT: movi.2s [[MASK:v[0-9]+]], #1
; CHECK-NEXT: and.8b v0, [[CMP]], [[MASK]]
; CHECK-NEXT: ret
@@ -23,9 +23,9 @@
define <2 x i32> @icmp_constfold_v2i32(<2 x i32> %a) {
; CHECK-LABEL: icmp_constfold_v2i32:
-; CHECK: ; BB#0:
+; CHECK: ; %bb.0:
; CHECK-NEXT: movi d[[CMP:[0-9]+]], #0xffffffffffffffff
-; CHECK-NEXT: ; BB#1:
+; CHECK-NEXT: ; %bb.1:
; CHECK-NEXT: movi.2s [[MASK:v[0-9]+]], #1
; CHECK-NEXT: and.8b v0, v[[CMP]], [[MASK]]
; CHECK-NEXT: ret
@@ -38,10 +38,10 @@
define <4 x i32> @icmp_v4i32(<4 x i32> %a) {
; CHECK-LABEL: icmp_v4i32:
-; CHECK: ; BB#0:
+; CHECK: ; %bb.0:
; CHECK-NEXT: cmeq.4s [[CMP:v[0-9]+]], v0, #0
; CHECK-NEXT: xtn.4h [[CMPV4I16:v[0-9]+]], [[CMP]]
-; CHECK-NEXT: ; BB#1:
+; CHECK-NEXT: ; %bb.1:
; CHECK-NEXT: movi.4h [[MASK:v[0-9]+]], #1
; CHECK-NEXT: and.8b [[ZEXT:v[0-9]+]], [[CMPV4I16]], [[MASK]]
; CHECK-NEXT: ushll.4s v0, [[ZEXT]], #0
@@ -55,9 +55,9 @@
define <4 x i32> @icmp_constfold_v4i32(<4 x i32> %a) {
; CHECK-LABEL: icmp_constfold_v4i32:
-; CHECK: ; BB#0:
+; CHECK: ; %bb.0:
; CHECK-NEXT: movi d[[CMP:[0-9]+]], #0xffffffffffffffff
-; CHECK-NEXT: ; BB#1:
+; CHECK-NEXT: ; %bb.1:
; CHECK-NEXT: movi.4h [[MASK:v[0-9]+]], #1
; CHECK-NEXT: and.8b [[ZEXT:v[0-9]+]], v[[CMP]], [[MASK]]
; CHECK-NEXT: ushll.4s v0, [[ZEXT]], #0
@@ -71,9 +71,9 @@
define <16 x i8> @icmp_v16i8(<16 x i8> %a) {
; CHECK-LABEL: icmp_v16i8:
-; CHECK: ; BB#0:
+; CHECK: ; %bb.0:
; CHECK-NEXT: cmeq.16b [[CMP:v[0-9]+]], v0, #0
-; CHECK-NEXT: ; BB#1:
+; CHECK-NEXT: ; %bb.1:
; CHECK-NEXT: movi.16b [[MASK:v[0-9]+]], #1
; CHECK-NEXT: and.16b v0, [[CMP]], [[MASK]]
; CHECK-NEXT: ret
@@ -86,9 +86,9 @@
define <16 x i8> @icmp_constfold_v16i8(<16 x i8> %a) {
; CHECK-LABEL: icmp_constfold_v16i8:
-; CHECK: ; BB#0:
+; CHECK: ; %bb.0:
; CHECK-NEXT: movi.2d [[CMP:v[0-9]+]], #0xffffffffffffffff
-; CHECK-NEXT: ; BB#1:
+; CHECK-NEXT: ; %bb.1:
; CHECK-NEXT: movi.16b [[MASK:v[0-9]+]], #1
; CHECK-NEXT: and.16b v0, [[CMP]], [[MASK]]
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/AArch64/fast-isel-cmpxchg.ll b/llvm/test/CodeGen/AArch64/fast-isel-cmpxchg.ll
index 7ef625a..f03955c 100644
--- a/llvm/test/CodeGen/AArch64/fast-isel-cmpxchg.ll
+++ b/llvm/test/CodeGen/AArch64/fast-isel-cmpxchg.ll
@@ -6,7 +6,7 @@
; CHECK-NEXT: ldaxr [[OLD:w[0-9]+]], [x0]
; CHECK-NEXT: cmp [[OLD]], w1
; CHECK-NEXT: b.ne [[DONE:.LBB[0-9_]+]]
-; CHECK-NEXT: // BB#2:
+; CHECK-NEXT: // %bb.2:
; CHECK-NEXT: stlxr [[STATUS]], w2, [x0]
; CHECK-NEXT: cbnz [[STATUS]], [[RETRY]]
; CHECK-NEXT: [[DONE]]:
@@ -25,14 +25,14 @@
}
; CHECK-LABEL: cmpxchg_acq_rel_32_load:
-; CHECK: // BB#0:
+; CHECK: // %bb.0:
; CHECK: ldr [[NEW:w[0-9]+]], [x2]
; CHECK-NEXT: [[RETRY:.LBB[0-9_]+]]:
; CHECK-NEXT: mov [[STATUS:w[0-9]+]], #0
; CHECK-NEXT: ldaxr [[OLD:w[0-9]+]], [x0]
; CHECK-NEXT: cmp [[OLD]], w1
; CHECK-NEXT: b.ne [[DONE:.LBB[0-9_]+]]
-; CHECK-NEXT: // BB#2:
+; CHECK-NEXT: // %bb.2:
; CHECK-NEXT: stlxr [[STATUS]], [[NEW]], [x0]
; CHECK-NEXT: cbnz [[STATUS]], [[RETRY]]
; CHECK-NEXT: [[DONE]]:
@@ -57,7 +57,7 @@
; CHECK-NEXT: ldaxr [[OLD:x[0-9]+]], [x0]
; CHECK-NEXT: cmp [[OLD]], x1
; CHECK-NEXT: b.ne [[DONE:.LBB[0-9_]+]]
-; CHECK-NEXT: // BB#2:
+; CHECK-NEXT: // %bb.2:
; CHECK-NEXT: stlxr [[STATUS]], x2, [x0]
; CHECK-NEXT: cbnz [[STATUS]], [[RETRY]]
; CHECK-NEXT: [[DONE]]:
diff --git a/llvm/test/CodeGen/AArch64/fcvt-int.ll b/llvm/test/CodeGen/AArch64/fcvt-int.ll
index e52b601..aeafc12 100644
--- a/llvm/test/CodeGen/AArch64/fcvt-int.ll
+++ b/llvm/test/CodeGen/AArch64/fcvt-int.ll
@@ -152,7 +152,7 @@
define double @bitcast_fabs(double %x) {
; CHECK-LABEL: bitcast_fabs:
-; CHECK: ; BB#0:
+; CHECK: ; %bb.0:
; CHECK-NEXT: fabs d0, d0
; CHECK-NEXT: ret
;
@@ -164,7 +164,7 @@
define float @bitcast_fneg(float %x) {
; CHECK-LABEL: bitcast_fneg:
-; CHECK: ; BB#0:
+; CHECK: ; %bb.0:
; CHECK-NEXT: fneg s0, s0
; CHECK-NEXT: ret
;
diff --git a/llvm/test/CodeGen/AArch64/local_vars.ll b/llvm/test/CodeGen/AArch64/local_vars.ll
index 6e33ab2..a479572 100644
--- a/llvm/test/CodeGen/AArch64/local_vars.ll
+++ b/llvm/test/CodeGen/AArch64/local_vars.ll
@@ -17,7 +17,7 @@
define void @trivial_func() nounwind {
; CHECK-LABEL: trivial_func: // @trivial_func
-; CHECK-NEXT: // BB#0
+; CHECK-NEXT: // %bb.0
; CHECK-NEXT: ret
ret void
diff --git a/llvm/test/CodeGen/AArch64/max-jump-table.ll b/llvm/test/CodeGen/AArch64/max-jump-table.ll
index 0705020..1a7a418 100644
--- a/llvm/test/CodeGen/AArch64/max-jump-table.ll
+++ b/llvm/test/CodeGen/AArch64/max-jump-table.ll
@@ -77,10 +77,10 @@
]
; CHECK-LABEL: function jt2:
; CHECK-NEXT: Jump Tables:
-; CHECK0-NEXT: jt#0: BB#1 BB#2 BB#3 BB#4 BB#7 BB#7 BB#7 BB#7 BB#7 BB#7 BB#7 BB#7 BB#7 BB#5 BB#6{{$}}
-; CHECK4-NEXT: jt#0: BB#1 BB#2 BB#3 BB#4{{$}}
-; CHECK8-NEXT: jt#0: BB#1 BB#2 BB#3 BB#4{{$}}
-; CHECKM1-NEXT: jt#0: BB#1 BB#2 BB#3 BB#4{{$}}
+; CHECK0-NEXT: jt#0: %bb.1 %bb.2 %bb.3 %bb.4 %bb.7 %bb.7 %bb.7 %bb.7 %bb.7 %bb.7 %bb.7 %bb.7 %bb.7 %bb.5 %bb.6{{$}}
+; CHECK4-NEXT: jt#0: %bb.1 %bb.2 %bb.3 %bb.4{{$}}
+; CHECK8-NEXT: jt#0: %bb.1 %bb.2 %bb.3 %bb.4{{$}}
+; CHECKM1-NEXT: jt#0: %bb.1 %bb.2 %bb.3 %bb.4{{$}}
; CHEC-NEXT: Function Live Ins:
bb1: tail call void @ext(i32 1) br label %return
diff --git a/llvm/test/CodeGen/AArch64/neon-bitcast.ll b/llvm/test/CodeGen/AArch64/neon-bitcast.ll
index 61099d4..8f67ff8 100644
--- a/llvm/test/CodeGen/AArch64/neon-bitcast.ll
+++ b/llvm/test/CodeGen/AArch64/neon-bitcast.ll
@@ -4,7 +4,7 @@
define <1 x i64> @test_v8i8_to_v1i64(<8 x i8> %in) nounwind {
; CHECK: test_v8i8_to_v1i64:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ret
%val = bitcast <8 x i8> %in to <1 x i64>
@@ -13,7 +13,7 @@
define <2 x i32> @test_v8i8_to_v2i32(<8 x i8> %in) nounwind {
; CHECK: test_v8i8_to_v2i32:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ret
%val = bitcast <8 x i8> %in to <2 x i32>
@@ -22,7 +22,7 @@
define <2 x float> @test_v8i8_to_v2f32(<8 x i8> %in) nounwind{
; CHECK: test_v8i8_to_v2f32:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ret
%val = bitcast <8 x i8> %in to <2 x float>
@@ -31,7 +31,7 @@
define <4 x i16> @test_v8i8_to_v4i16(<8 x i8> %in) nounwind{
; CHECK: test_v8i8_to_v4i16:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ret
%val = bitcast <8 x i8> %in to <4 x i16>
@@ -40,7 +40,7 @@
define <8 x i8> @test_v8i8_to_v8i8(<8 x i8> %in) nounwind{
; CHECK: test_v8i8_to_v8i8:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ret
%val = bitcast <8 x i8> %in to <8 x i8>
@@ -51,7 +51,7 @@
define <1 x i64> @test_v4i16_to_v1i64(<4 x i16> %in) nounwind {
; CHECK: test_v4i16_to_v1i64:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ret
%val = bitcast <4 x i16> %in to <1 x i64>
@@ -60,7 +60,7 @@
define <2 x i32> @test_v4i16_to_v2i32(<4 x i16> %in) nounwind {
; CHECK: test_v4i16_to_v2i32:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ret
%val = bitcast <4 x i16> %in to <2 x i32>
@@ -69,7 +69,7 @@
define <2 x float> @test_v4i16_to_v2f32(<4 x i16> %in) nounwind{
; CHECK: test_v4i16_to_v2f32:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ret
%val = bitcast <4 x i16> %in to <2 x float>
@@ -78,7 +78,7 @@
define <4 x i16> @test_v4i16_to_v4i16(<4 x i16> %in) nounwind{
; CHECK: test_v4i16_to_v4i16:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ret
%val = bitcast <4 x i16> %in to <4 x i16>
@@ -87,7 +87,7 @@
define <8 x i8> @test_v4i16_to_v8i8(<4 x i16> %in) nounwind{
; CHECK: test_v4i16_to_v8i8:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ret
%val = bitcast <4 x i16> %in to <8 x i8>
@@ -98,7 +98,7 @@
define <1 x i64> @test_v2i32_to_v1i64(<2 x i32> %in) nounwind {
; CHECK: test_v2i32_to_v1i64:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ret
%val = bitcast <2 x i32> %in to <1 x i64>
@@ -107,7 +107,7 @@
define <2 x i32> @test_v2i32_to_v2i32(<2 x i32> %in) nounwind {
; CHECK: test_v2i32_to_v2i32:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ret
%val = bitcast <2 x i32> %in to <2 x i32>
@@ -116,7 +116,7 @@
define <2 x float> @test_v2i32_to_v2f32(<2 x i32> %in) nounwind{
; CHECK: test_v2i32_to_v2f32:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ret
%val = bitcast <2 x i32> %in to <2 x float>
@@ -125,7 +125,7 @@
define <4 x i16> @test_v2i32_to_v4i16(<2 x i32> %in) nounwind{
; CHECK: test_v2i32_to_v4i16:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ret
%val = bitcast <2 x i32> %in to <4 x i16>
@@ -134,7 +134,7 @@
define <8 x i8> @test_v2i32_to_v8i8(<2 x i32> %in) nounwind{
; CHECK: test_v2i32_to_v8i8:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ret
%val = bitcast <2 x i32> %in to <8 x i8>
@@ -145,7 +145,7 @@
define <1 x i64> @test_v2f32_to_v1i64(<2 x float> %in) nounwind {
; CHECK: test_v2f32_to_v1i64:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ret
%val = bitcast <2 x float> %in to <1 x i64>
@@ -154,7 +154,7 @@
define <2 x i32> @test_v2f32_to_v2i32(<2 x float> %in) nounwind {
; CHECK: test_v2f32_to_v2i32:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ret
%val = bitcast <2 x float> %in to <2 x i32>
@@ -163,7 +163,7 @@
define <2 x float> @test_v2f32_to_v2f32(<2 x float> %in) nounwind{
; CHECK: test_v2f32_to_v2f32:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ret
%val = bitcast <2 x float> %in to <2 x float>
@@ -172,7 +172,7 @@
define <4 x i16> @test_v2f32_to_v4i16(<2 x float> %in) nounwind{
; CHECK: test_v2f32_to_v4i16:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ret
%val = bitcast <2 x float> %in to <4 x i16>
@@ -181,7 +181,7 @@
define <8 x i8> @test_v2f32_to_v8i8(<2 x float> %in) nounwind{
; CHECK: test_v2f32_to_v8i8:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ret
%val = bitcast <2 x float> %in to <8 x i8>
@@ -192,7 +192,7 @@
define <1 x i64> @test_v1i64_to_v1i64(<1 x i64> %in) nounwind {
; CHECK: test_v1i64_to_v1i64:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ret
%val = bitcast <1 x i64> %in to <1 x i64>
@@ -201,7 +201,7 @@
define <2 x i32> @test_v1i64_to_v2i32(<1 x i64> %in) nounwind {
; CHECK: test_v1i64_to_v2i32:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ret
%val = bitcast <1 x i64> %in to <2 x i32>
@@ -210,7 +210,7 @@
define <2 x float> @test_v1i64_to_v2f32(<1 x i64> %in) nounwind{
; CHECK: test_v1i64_to_v2f32:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ret
%val = bitcast <1 x i64> %in to <2 x float>
@@ -219,7 +219,7 @@
define <4 x i16> @test_v1i64_to_v4i16(<1 x i64> %in) nounwind{
; CHECK: test_v1i64_to_v4i16:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ret
%val = bitcast <1 x i64> %in to <4 x i16>
@@ -228,7 +228,7 @@
define <8 x i8> @test_v1i64_to_v8i8(<1 x i64> %in) nounwind{
; CHECK: test_v1i64_to_v8i8:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ret
%val = bitcast <1 x i64> %in to <8 x i8>
@@ -240,7 +240,7 @@
define <2 x double> @test_v16i8_to_v2f64(<16 x i8> %in) nounwind {
; CHECK: test_v16i8_to_v2f64:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ret
%val = bitcast <16 x i8> %in to <2 x double>
@@ -249,7 +249,7 @@
define <2 x i64> @test_v16i8_to_v2i64(<16 x i8> %in) nounwind {
; CHECK: test_v16i8_to_v2i64:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ret
%val = bitcast <16 x i8> %in to <2 x i64>
@@ -258,7 +258,7 @@
define <4 x i32> @test_v16i8_to_v4i32(<16 x i8> %in) nounwind {
; CHECK: test_v16i8_to_v4i32:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ret
%val = bitcast <16 x i8> %in to <4 x i32>
@@ -267,7 +267,7 @@
define <4 x float> @test_v16i8_to_v2f32(<16 x i8> %in) nounwind{
; CHECK: test_v16i8_to_v2f32:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ret
%val = bitcast <16 x i8> %in to <4 x float>
@@ -276,7 +276,7 @@
define <8 x i16> @test_v16i8_to_v8i16(<16 x i8> %in) nounwind{
; CHECK: test_v16i8_to_v8i16:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ret
%val = bitcast <16 x i8> %in to <8 x i16>
@@ -285,7 +285,7 @@
define <16 x i8> @test_v16i8_to_v16i8(<16 x i8> %in) nounwind{
; CHECK: test_v16i8_to_v16i8:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ret
%val = bitcast <16 x i8> %in to <16 x i8>
@@ -296,7 +296,7 @@
define <2 x double> @test_v8i16_to_v2f64(<8 x i16> %in) nounwind {
; CHECK: test_v8i16_to_v2f64:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ret
%val = bitcast <8 x i16> %in to <2 x double>
@@ -305,7 +305,7 @@
define <2 x i64> @test_v8i16_to_v2i64(<8 x i16> %in) nounwind {
; CHECK: test_v8i16_to_v2i64:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ret
%val = bitcast <8 x i16> %in to <2 x i64>
@@ -314,7 +314,7 @@
define <4 x i32> @test_v8i16_to_v4i32(<8 x i16> %in) nounwind {
; CHECK: test_v8i16_to_v4i32:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ret
%val = bitcast <8 x i16> %in to <4 x i32>
@@ -323,7 +323,7 @@
define <4 x float> @test_v8i16_to_v2f32(<8 x i16> %in) nounwind{
; CHECK: test_v8i16_to_v2f32:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ret
%val = bitcast <8 x i16> %in to <4 x float>
@@ -332,7 +332,7 @@
define <8 x i16> @test_v8i16_to_v8i16(<8 x i16> %in) nounwind{
; CHECK: test_v8i16_to_v8i16:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ret
%val = bitcast <8 x i16> %in to <8 x i16>
@@ -341,7 +341,7 @@
define <16 x i8> @test_v8i16_to_v16i8(<8 x i16> %in) nounwind{
; CHECK: test_v8i16_to_v16i8:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ret
%val = bitcast <8 x i16> %in to <16 x i8>
@@ -352,7 +352,7 @@
define <2 x double> @test_v4i32_to_v2f64(<4 x i32> %in) nounwind {
; CHECK: test_v4i32_to_v2f64:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ret
%val = bitcast <4 x i32> %in to <2 x double>
@@ -361,7 +361,7 @@
define <2 x i64> @test_v4i32_to_v2i64(<4 x i32> %in) nounwind {
; CHECK: test_v4i32_to_v2i64:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ret
%val = bitcast <4 x i32> %in to <2 x i64>
@@ -370,7 +370,7 @@
define <4 x i32> @test_v4i32_to_v4i32(<4 x i32> %in) nounwind {
; CHECK: test_v4i32_to_v4i32:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ret
%val = bitcast <4 x i32> %in to <4 x i32>
@@ -379,7 +379,7 @@
define <4 x float> @test_v4i32_to_v2f32(<4 x i32> %in) nounwind{
; CHECK: test_v4i32_to_v2f32:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ret
%val = bitcast <4 x i32> %in to <4 x float>
@@ -388,7 +388,7 @@
define <8 x i16> @test_v4i32_to_v8i16(<4 x i32> %in) nounwind{
; CHECK: test_v4i32_to_v8i16:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ret
%val = bitcast <4 x i32> %in to <8 x i16>
@@ -397,7 +397,7 @@
define <16 x i8> @test_v4i32_to_v16i8(<4 x i32> %in) nounwind{
; CHECK: test_v4i32_to_v16i8:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ret
%val = bitcast <4 x i32> %in to <16 x i8>
@@ -408,7 +408,7 @@
define <2 x double> @test_v4f32_to_v2f64(<4 x float> %in) nounwind {
; CHECK: test_v4f32_to_v2f64:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ret
%val = bitcast <4 x float> %in to <2 x double>
@@ -417,7 +417,7 @@
define <2 x i64> @test_v4f32_to_v2i64(<4 x float> %in) nounwind {
; CHECK: test_v4f32_to_v2i64:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ret
%val = bitcast <4 x float> %in to <2 x i64>
@@ -426,7 +426,7 @@
define <4 x i32> @test_v4f32_to_v4i32(<4 x float> %in) nounwind {
; CHECK: test_v4f32_to_v4i32:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ret
%val = bitcast <4 x float> %in to <4 x i32>
@@ -435,7 +435,7 @@
define <4 x float> @test_v4f32_to_v4f32(<4 x float> %in) nounwind{
; CHECK: test_v4f32_to_v4f32:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ret
%val = bitcast <4 x float> %in to <4 x float>
@@ -444,7 +444,7 @@
define <8 x i16> @test_v4f32_to_v8i16(<4 x float> %in) nounwind{
; CHECK: test_v4f32_to_v8i16:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ret
%val = bitcast <4 x float> %in to <8 x i16>
@@ -453,7 +453,7 @@
define <16 x i8> @test_v4f32_to_v16i8(<4 x float> %in) nounwind{
; CHECK: test_v4f32_to_v16i8:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ret
%val = bitcast <4 x float> %in to <16 x i8>
@@ -464,7 +464,7 @@
define <2 x double> @test_v2i64_to_v2f64(<2 x i64> %in) nounwind {
; CHECK: test_v2i64_to_v2f64:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ret
%val = bitcast <2 x i64> %in to <2 x double>
@@ -473,7 +473,7 @@
define <2 x i64> @test_v2i64_to_v2i64(<2 x i64> %in) nounwind {
; CHECK: test_v2i64_to_v2i64:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ret
%val = bitcast <2 x i64> %in to <2 x i64>
@@ -482,7 +482,7 @@
define <4 x i32> @test_v2i64_to_v4i32(<2 x i64> %in) nounwind {
; CHECK: test_v2i64_to_v4i32:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ret
%val = bitcast <2 x i64> %in to <4 x i32>
@@ -491,7 +491,7 @@
define <4 x float> @test_v2i64_to_v4f32(<2 x i64> %in) nounwind{
; CHECK: test_v2i64_to_v4f32:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ret
%val = bitcast <2 x i64> %in to <4 x float>
@@ -500,7 +500,7 @@
define <8 x i16> @test_v2i64_to_v8i16(<2 x i64> %in) nounwind{
; CHECK: test_v2i64_to_v8i16:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ret
%val = bitcast <2 x i64> %in to <8 x i16>
@@ -509,7 +509,7 @@
define <16 x i8> @test_v2i64_to_v16i8(<2 x i64> %in) nounwind{
; CHECK: test_v2i64_to_v16i8:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ret
%val = bitcast <2 x i64> %in to <16 x i8>
@@ -520,7 +520,7 @@
define <2 x double> @test_v2f64_to_v2f64(<2 x double> %in) nounwind {
; CHECK: test_v2f64_to_v2f64:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ret
%val = bitcast <2 x double> %in to <2 x double>
@@ -529,7 +529,7 @@
define <2 x i64> @test_v2f64_to_v2i64(<2 x double> %in) nounwind {
; CHECK: test_v2f64_to_v2i64:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ret
%val = bitcast <2 x double> %in to <2 x i64>
@@ -538,7 +538,7 @@
define <4 x i32> @test_v2f64_to_v4i32(<2 x double> %in) nounwind {
; CHECK: test_v2f64_to_v4i32:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ret
%val = bitcast <2 x double> %in to <4 x i32>
@@ -547,7 +547,7 @@
define <4 x float> @test_v2f64_to_v4f32(<2 x double> %in) nounwind{
; CHECK: test_v2f64_to_v4f32:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ret
%val = bitcast <2 x double> %in to <4 x float>
@@ -556,7 +556,7 @@
define <8 x i16> @test_v2f64_to_v8i16(<2 x double> %in) nounwind{
; CHECK: test_v2f64_to_v8i16:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ret
%val = bitcast <2 x double> %in to <8 x i16>
@@ -565,7 +565,7 @@
define <16 x i8> @test_v2f64_to_v16i8(<2 x double> %in) nounwind{
; CHECK: test_v2f64_to_v16i8:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ret
%val = bitcast <2 x double> %in to <16 x i8>
diff --git a/llvm/test/CodeGen/AArch64/nest-register.ll b/llvm/test/CodeGen/AArch64/nest-register.ll
index cc42913..b865171 100644
--- a/llvm/test/CodeGen/AArch64/nest-register.ll
+++ b/llvm/test/CodeGen/AArch64/nest-register.ll
@@ -5,7 +5,7 @@
define i8* @nest_receiver(i8* nest %arg) nounwind {
; CHECK-LABEL: nest_receiver:
-; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: mov x0, x18
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/AArch64/recp-fastmath.ll b/llvm/test/CodeGen/AArch64/recp-fastmath.ll
index 4776931..9f00621 100644
--- a/llvm/test/CodeGen/AArch64/recp-fastmath.ll
+++ b/llvm/test/CodeGen/AArch64/recp-fastmath.ll
@@ -5,7 +5,7 @@
ret float %div
; CHECK-LABEL: frecp0:
-; CHECK-NEXT: BB#0
+; CHECK-NEXT: %bb.0
; CHECK-NEXT: fmov
; CHECK-NEXT: fdiv
}
@@ -15,7 +15,7 @@
ret float %div
; CHECK-LABEL: frecp1:
-; CHECK-NEXT: BB#0
+; CHECK-NEXT: %bb.0
; CHECK-NEXT: frecpe [[R:s[0-7]]]
; CHECK-NEXT: frecps {{s[0-7](, s[0-7])?}}, [[R]]
; CHECK: frecps {{s[0-7]}}, {{s[0-7]}}, {{s[0-7]}}
@@ -27,7 +27,7 @@
ret <2 x float> %div
; CHECK-LABEL: f2recp0:
-; CHECK-NEXT: BB#0
+; CHECK-NEXT: %bb.0
; CHECK-NEXT: fmov
; CHECK-NEXT: fdiv
}
@@ -37,7 +37,7 @@
ret <2 x float> %div
; CHECK-LABEL: f2recp1:
-; CHECK-NEXT: BB#0
+; CHECK-NEXT: %bb.0
; CHECK-NEXT: frecpe [[R:v[0-7]\.2s]]
; CHECK-NEXT: frecps {{v[0-7]\.2s(, v[0-7].2s)?}}, [[R]]
; CHECK: frecps {{v[0-7]\.2s}}, {{v[0-7]\.2s}}, {{v[0-7]\.2s}}
@@ -49,7 +49,7 @@
ret <4 x float> %div
; CHECK-LABEL: f4recp0:
-; CHECK-NEXT: BB#0
+; CHECK-NEXT: %bb.0
; CHECK-NEXT: fmov
; CHECK-NEXT: fdiv
}
@@ -59,7 +59,7 @@
ret <4 x float> %div
; CHECK-LABEL: f4recp1:
-; CHECK-NEXT: BB#0
+; CHECK-NEXT: %bb.0
; CHECK-NEXT: frecpe [[R:v[0-7]\.4s]]
; CHECK-NEXT: frecps {{v[0-7]\.4s(, v[0-7].4s)?}}, [[R]]
; CHECK: frecps {{v[0-7]\.4s}}, {{v[0-7]\.4s}}, {{v[0-7]\.4s}}
@@ -71,7 +71,7 @@
ret <8 x float> %div
; CHECK-LABEL: f8recp0:
-; CHECK-NEXT: BB#0
+; CHECK-NEXT: %bb.0
; CHECK-NEXT: fmov
; CHECK-NEXT: fdiv
; CHECK-NEXT: fdiv
@@ -82,7 +82,7 @@
ret <8 x float> %div
; CHECK-LABEL: f8recp1:
-; CHECK-NEXT: BB#0
+; CHECK-NEXT: %bb.0
; CHECK-NEXT: frecpe [[R:v[0-7]\.4s]]
; CHECK: frecps {{v[0-7]\.4s(, v[0-7].4s)?}}, [[R]]
; CHECK: frecps {{v[0-7]\.4s(, v[0-7].4s)?}}, {{v[0-7]\.4s}}
@@ -96,7 +96,7 @@
ret double %div
; CHECK-LABEL: drecp0:
-; CHECK-NEXT: BB#0
+; CHECK-NEXT: %bb.0
; CHECK-NEXT: fmov
; CHECK-NEXT: fdiv
}
@@ -106,7 +106,7 @@
ret double %div
; CHECK-LABEL: drecp1:
-; CHECK-NEXT: BB#0
+; CHECK-NEXT: %bb.0
; CHECK-NEXT: frecpe [[R:d[0-7]]]
; CHECK-NEXT: frecps {{d[0-7](, d[0-7])?}}, [[R]]
; CHECK: frecps {{d[0-7]}}, {{d[0-7]}}, {{d[0-7]}}
@@ -119,7 +119,7 @@
ret <2 x double> %div
; CHECK-LABEL: d2recp0:
-; CHECK-NEXT: BB#0
+; CHECK-NEXT: %bb.0
; CHECK-NEXT: fmov
; CHECK-NEXT: fdiv
}
@@ -129,7 +129,7 @@
ret <2 x double> %div
; CHECK-LABEL: d2recp1:
-; CHECK-NEXT: BB#0
+; CHECK-NEXT: %bb.0
; CHECK-NEXT: frecpe [[R:v[0-7]\.2d]]
; CHECK-NEXT: frecps {{v[0-7]\.2d(, v[0-7].2d)?}}, [[R]]
; CHECK: frecps {{v[0-7]\.2d}}, {{v[0-7]\.2d}}, {{v[0-7]\.2d}}
@@ -142,7 +142,7 @@
ret <4 x double> %div
; CHECK-LABEL: d4recp0:
-; CHECK-NEXT: BB#0
+; CHECK-NEXT: %bb.0
; CHECK-NEXT: fmov
; CHECK-NEXT: fdiv
; CHECK-NEXT: fdiv
@@ -153,7 +153,7 @@
ret <4 x double> %div
; CHECK-LABEL: d4recp1:
-; CHECK-NEXT: BB#0
+; CHECK-NEXT: %bb.0
; CHECK-NEXT: frecpe [[R:v[0-7]\.2d]]
; CHECK: frecps {{v[0-7]\.2d(, v[0-7].2d)?}}, [[R]]
; CHECK: frecps {{v[0-7]\.2d}}, {{v[0-7]\.2d}}, {{v[0-7]\.2d}}
diff --git a/llvm/test/CodeGen/AArch64/selectcc-to-shiftand.ll b/llvm/test/CodeGen/AArch64/selectcc-to-shiftand.ll
index 0d89cde..9919063 100644
--- a/llvm/test/CodeGen/AArch64/selectcc-to-shiftand.ll
+++ b/llvm/test/CodeGen/AArch64/selectcc-to-shiftand.ll
@@ -4,7 +4,7 @@
define i32 @neg_sel_constants(i32 %a) {
; CHECK-LABEL: neg_sel_constants:
-; CHECK: // BB#0:
+; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #5
; CHECK-NEXT: and w0, w8, w0, asr #31
; CHECK-NEXT: ret
@@ -18,7 +18,7 @@
define i32 @neg_sel_special_constant(i32 %a) {
; CHECK-LABEL: neg_sel_special_constant:
-; CHECK: // BB#0:
+; CHECK: // %bb.0:
; CHECK-NEXT: lsr w8, w0, #22
; CHECK-NEXT: and w0, w8, #0x200
; CHECK-NEXT: ret
@@ -32,7 +32,7 @@
define i32 @neg_sel_variable_and_zero(i32 %a, i32 %b) {
; CHECK-LABEL: neg_sel_variable_and_zero:
-; CHECK: // BB#0:
+; CHECK: // %bb.0:
; CHECK-NEXT: and w0, w1, w0, asr #31
; CHECK-NEXT: ret
;
@@ -45,7 +45,7 @@
define i32 @not_pos_sel_same_variable(i32 %a) {
; CHECK-LABEL: not_pos_sel_same_variable:
-; CHECK: // BB#0:
+; CHECK: // %bb.0:
; CHECK-NEXT: and w0, w0, w0, asr #31
; CHECK-NEXT: ret
;
@@ -60,7 +60,7 @@
define i32 @pos_sel_constants(i32 %a) {
; CHECK-LABEL: pos_sel_constants:
-; CHECK: // BB#0:
+; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #5
; CHECK-NEXT: bic w0, w8, w0, asr #31
; CHECK-NEXT: ret
@@ -74,7 +74,7 @@
define i32 @pos_sel_special_constant(i32 %a) {
; CHECK-LABEL: pos_sel_special_constant:
-; CHECK: // BB#0:
+; CHECK: // %bb.0:
; CHECK-NEXT: orr w8, wzr, #0x200
; CHECK-NEXT: bic w0, w8, w0, lsr #22
; CHECK-NEXT: ret
@@ -88,7 +88,7 @@
define i32 @pos_sel_variable_and_zero(i32 %a, i32 %b) {
; CHECK-LABEL: pos_sel_variable_and_zero:
-; CHECK: // BB#0:
+; CHECK: // %bb.0:
; CHECK-NEXT: bic w0, w1, w0, asr #31
; CHECK-NEXT: ret
;
@@ -101,7 +101,7 @@
define i32 @not_neg_sel_same_variable(i32 %a) {
; CHECK-LABEL: not_neg_sel_same_variable:
-; CHECK: // BB#0:
+; CHECK: // %bb.0:
; CHECK-NEXT: bic w0, w0, w0, asr #31
; CHECK-NEXT: ret
;
@@ -115,7 +115,7 @@
; ret = (x-y) > 0 ? x-y : 0
define i32 @PR31175(i32 %x, i32 %y) {
; CHECK-LABEL: PR31175:
-; CHECK: // BB#0:
+; CHECK: // %bb.0:
; CHECK-NEXT: sub w8, w0, w1
; CHECK-NEXT: bic w0, w8, w8, asr #31
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/AArch64/sibling-call.ll b/llvm/test/CodeGen/AArch64/sibling-call.ll
index 9a44b43..be59f27 100644
--- a/llvm/test/CodeGen/AArch64/sibling-call.ll
+++ b/llvm/test/CodeGen/AArch64/sibling-call.ll
@@ -6,7 +6,7 @@
define void @caller_to0_from0() nounwind {
; CHECK-LABEL: caller_to0_from0:
-; CHECK-NEXT: // BB
+; CHECK-NEXT: // %bb.
tail call void @callee_stack0()
ret void
; CHECK-NEXT: b callee_stack0
@@ -14,7 +14,7 @@
define void @caller_to0_from8([8 x i32], i64) nounwind{
; CHECK-LABEL: caller_to0_from8:
-; CHECK-NEXT: // BB
+; CHECK-NEXT: // %bb.
tail call void @callee_stack0()
ret void
diff --git a/llvm/test/CodeGen/AArch64/sqrt-fastmath.ll b/llvm/test/CodeGen/AArch64/sqrt-fastmath.ll
index 4dd0516..ade9e3d 100644
--- a/llvm/test/CodeGen/AArch64/sqrt-fastmath.ll
+++ b/llvm/test/CodeGen/AArch64/sqrt-fastmath.ll
@@ -14,11 +14,11 @@
ret float %1
; FAULT-LABEL: fsqrt:
-; FAULT-NEXT: BB#0
+; FAULT-NEXT: %bb.0
; FAULT-NEXT: fsqrt
; CHECK-LABEL: fsqrt:
-; CHECK-NEXT: BB#0
+; CHECK-NEXT: %bb.0
; CHECK-NEXT: frsqrte [[RA:s[0-7]]]
; CHECK-NEXT: fmul [[RB:s[0-7]]], [[RA]], [[RA]]
; CHECK-NEXT: frsqrts {{s[0-7](, s[0-7])?}}, [[RB]]
@@ -32,11 +32,11 @@
ret <2 x float> %1
; FAULT-LABEL: f2sqrt:
-; FAULT-NEXT: BB#0
+; FAULT-NEXT: %bb.0
; FAULT-NEXT: fsqrt
; CHECK-LABEL: f2sqrt:
-; CHECK-NEXT: BB#0
+; CHECK-NEXT: %bb.0
; CHECK-NEXT: frsqrte [[RA:v[0-7]\.2s]]
; CHECK-NEXT: fmul [[RB:v[0-7]\.2s]], [[RA]], [[RA]]
; CHECK-NEXT: frsqrts {{v[0-7]\.2s(, v[0-7]\.2s)?}}, [[RB]]
@@ -50,11 +50,11 @@
ret <4 x float> %1
; FAULT-LABEL: f4sqrt:
-; FAULT-NEXT: BB#0
+; FAULT-NEXT: %bb.0
; FAULT-NEXT: fsqrt
; CHECK-LABEL: f4sqrt:
-; CHECK-NEXT: BB#0
+; CHECK-NEXT: %bb.0
; CHECK-NEXT: frsqrte [[RA:v[0-7]\.4s]]
; CHECK-NEXT: fmul [[RB:v[0-7]\.4s]], [[RA]], [[RA]]
; CHECK-NEXT: frsqrts {{v[0-7]\.4s(, v[0-7]\.4s)?}}, [[RB]]
@@ -68,12 +68,12 @@
ret <8 x float> %1
; FAULT-LABEL: f8sqrt:
-; FAULT-NEXT: BB#0
+; FAULT-NEXT: %bb.0
; FAULT-NEXT: fsqrt
; FAULT-NEXT: fsqrt
; CHECK-LABEL: f8sqrt:
-; CHECK-NEXT: BB#0
+; CHECK-NEXT: %bb.0
; CHECK-NEXT: frsqrte [[RA:v[0-7]\.4s]]
; CHECK-NEXT: fmul [[RB:v[0-7]\.4s]], [[RA]], [[RA]]
; CHECK-NEXT: frsqrts {{v[0-7]\.4s(, v[0-7]\.4s)?}}, [[RB]]
@@ -92,11 +92,11 @@
ret double %1
; FAULT-LABEL: dsqrt:
-; FAULT-NEXT: BB#0
+; FAULT-NEXT: %bb.0
; FAULT-NEXT: fsqrt
; CHECK-LABEL: dsqrt:
-; CHECK-NEXT: BB#0
+; CHECK-NEXT: %bb.0
; CHECK-NEXT: frsqrte [[RA:d[0-7]]]
; CHECK-NEXT: fmul [[RB:d[0-7]]], [[RA]], [[RA]]
; CHECK-NEXT: frsqrts {{d[0-7](, d[0-7])?}}, [[RB]]
@@ -111,11 +111,11 @@
ret <2 x double> %1
; FAULT-LABEL: d2sqrt:
-; FAULT-NEXT: BB#0
+; FAULT-NEXT: %bb.0
; FAULT-NEXT: fsqrt
; CHECK-LABEL: d2sqrt:
-; CHECK-NEXT: BB#0
+; CHECK-NEXT: %bb.0
; CHECK-NEXT: frsqrte [[RA:v[0-7]\.2d]]
; CHECK-NEXT: fmul [[RB:v[0-7]\.2d]], [[RA]], [[RA]]
; CHECK-NEXT: frsqrts {{v[0-7]\.2d(, v[0-7]\.2d)?}}, [[RB]]
@@ -130,12 +130,12 @@
ret <4 x double> %1
; FAULT-LABEL: d4sqrt:
-; FAULT-NEXT: BB#0
+; FAULT-NEXT: %bb.0
; FAULT-NEXT: fsqrt
; FAULT-NEXT: fsqrt
; CHECK-LABEL: d4sqrt:
-; CHECK-NEXT: BB#0
+; CHECK-NEXT: %bb.0
; CHECK-NEXT: frsqrte [[RA:v[0-7]\.2d]]
; CHECK-NEXT: fmul [[RB:v[0-7]\.2d]], [[RA]], [[RA]]
; CHECK-NEXT: frsqrts {{v[0-7]\.2d(, v[0-7]\.2d)?}}, [[RB]]
@@ -158,11 +158,11 @@
ret float %2
; FAULT-LABEL: frsqrt:
-; FAULT-NEXT: BB#0
+; FAULT-NEXT: %bb.0
; FAULT-NEXT: fsqrt
; CHECK-LABEL: frsqrt:
-; CHECK-NEXT: BB#0
+; CHECK-NEXT: %bb.0
; CHECK-NEXT: frsqrte [[RA:s[0-7]]]
; CHECK-NEXT: fmul [[RB:s[0-7]]], [[RA]], [[RA]]
; CHECK-NEXT: frsqrts {{s[0-7](, s[0-7])?}}, [[RB]]
@@ -177,11 +177,11 @@
ret <2 x float> %2
; FAULT-LABEL: f2rsqrt:
-; FAULT-NEXT: BB#0
+; FAULT-NEXT: %bb.0
; FAULT-NEXT: fsqrt
; CHECK-LABEL: f2rsqrt:
-; CHECK-NEXT: BB#0
+; CHECK-NEXT: %bb.0
; CHECK-NEXT: frsqrte [[RA:v[0-7]\.2s]]
; CHECK-NEXT: fmul [[RB:v[0-7]\.2s]], [[RA]], [[RA]]
; CHECK-NEXT: frsqrts {{v[0-7]\.2s(, v[0-7]\.2s)?}}, [[RB]]
@@ -196,11 +196,11 @@
ret <4 x float> %2
; FAULT-LABEL: f4rsqrt:
-; FAULT-NEXT: BB#0
+; FAULT-NEXT: %bb.0
; FAULT-NEXT: fsqrt
; CHECK-LABEL: f4rsqrt:
-; CHECK-NEXT: BB#0
+; CHECK-NEXT: %bb.0
; CHECK-NEXT: frsqrte [[RA:v[0-7]\.4s]]
; CHECK-NEXT: fmul [[RB:v[0-7]\.4s]], [[RA]], [[RA]]
; CHECK-NEXT: frsqrts {{v[0-7]\.4s(, v[0-7]\.4s)?}}, [[RB]]
@@ -215,12 +215,12 @@
ret <8 x float> %2
; FAULT-LABEL: f8rsqrt:
-; FAULT-NEXT: BB#0
+; FAULT-NEXT: %bb.0
; FAULT-NEXT: fsqrt
; FAULT-NEXT: fsqrt
; CHECK-LABEL: f8rsqrt:
-; CHECK-NEXT: BB#0
+; CHECK-NEXT: %bb.0
; CHECK-NEXT: frsqrte [[RA:v[0-7]\.4s]]
; CHECK: fmul [[RB:v[0-7]\.4s]], [[RA]], [[RA]]
; CHECK: frsqrts {{v[0-7]\.4s(, v[0-7]\.4s)?}}, [[RB]]
@@ -237,11 +237,11 @@
ret double %2
; FAULT-LABEL: drsqrt:
-; FAULT-NEXT: BB#0
+; FAULT-NEXT: %bb.0
; FAULT-NEXT: fsqrt
; CHECK-LABEL: drsqrt:
-; CHECK-NEXT: BB#0
+; CHECK-NEXT: %bb.0
; CHECK-NEXT: frsqrte [[RA:d[0-7]]]
; CHECK-NEXT: fmul [[RB:d[0-7]]], [[RA]], [[RA]]
; CHECK-NEXT: frsqrts {{d[0-7](, d[0-7])?}}, [[RB]]
@@ -257,11 +257,11 @@
ret <2 x double> %2
; FAULT-LABEL: d2rsqrt:
-; FAULT-NEXT: BB#0
+; FAULT-NEXT: %bb.0
; FAULT-NEXT: fsqrt
; CHECK-LABEL: d2rsqrt:
-; CHECK-NEXT: BB#0
+; CHECK-NEXT: %bb.0
; CHECK-NEXT: frsqrte [[RA:v[0-7]\.2d]]
; CHECK-NEXT: fmul [[RB:v[0-7]\.2d]], [[RA]], [[RA]]
; CHECK-NEXT: frsqrts {{v[0-7]\.2d(, v[0-7]\.2d)?}}, [[RB]]
@@ -277,12 +277,12 @@
ret <4 x double> %2
; FAULT-LABEL: d4rsqrt:
-; FAULT-NEXT: BB#0
+; FAULT-NEXT: %bb.0
; FAULT-NEXT: fsqrt
; FAULT-NEXT: fsqrt
; CHECK-LABEL: d4rsqrt:
-; CHECK-NEXT: BB#0
+; CHECK-NEXT: %bb.0
; CHECK-NEXT: frsqrte [[RA:v[0-7]\.2d]]
; CHECK: fmul [[RB:v[0-7]\.2d]], [[RA]], [[RA]]
; CHECK: frsqrts {{v[0-7]\.2d(, v[0-7]\.2d)?}}, [[RB]]
diff --git a/llvm/test/CodeGen/AArch64/tail-call.ll b/llvm/test/CodeGen/AArch64/tail-call.ll
index fa5d8b9..ab63413 100644
--- a/llvm/test/CodeGen/AArch64/tail-call.ll
+++ b/llvm/test/CodeGen/AArch64/tail-call.ll
@@ -7,7 +7,7 @@
define fastcc void @caller_to0_from0() nounwind {
; CHECK-LABEL: caller_to0_from0:
-; CHECK-NEXT: // BB
+; CHECK-NEXT: // %bb.
tail call fastcc void @callee_stack0()
ret void