commit 2675a3c8806a0995f204efe999db6001f6e700cf
author Florian Hahn <flo@fhahn.com> Wed Dec 11 17:17:29 2019 +0000
committer Florian Hahn <flo@fhahn.com> Wed Dec 11 18:47:45 2019 +0000
tree 2ded52c7aa1d053797e2e2ad56cac1650a14514d
parent db76588964ee255da1f32b06565a2cd899a82947

[AArch64] Be more careful to skip debug operands in LdSt Optimizier.

This fixes crashes with $noreg operands.

llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp

diff --git a/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp b/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
index 2ffeea8..1bf882b 100644
--- a/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
+++ b/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
@@ -813,7 +813,7 @@
     --Limit;
 
     bool isDef = any_of(I->operands(), [DefReg, TRI](MachineOperand &MOP) {
-      return MOP.isReg() && MOP.isDef() &&
+      return MOP.isReg() && MOP.isDef() && !MOP.isDebug() && MOP.getReg() &&
              TRI->regsOverlap(MOP.getReg(), DefReg);
     });
     if (!Fn(*I, isDef))
@@ -880,7 +880,7 @@
             for (auto &MOP : MI.operands()) {
               // Rename the first explicit definition and all implicit
               // definitions matching RegToRename.
-              if (MOP.isReg() &&
+              if (MOP.isReg() && !MOP.isDebug() && MOP.getReg() &&
                   (!SeenDef || (MOP.isDef() && MOP.isImplicit())) &&
                   TRI->regsOverlap(MOP.getReg(), RegToRename)) {
                 assert((MOP.isImplicit() ||
@@ -892,7 +892,8 @@
             }
           } else {
             for (auto &MOP : MI.operands()) {
-              if (MOP.isReg() && TRI->regsOverlap(MOP.getReg(), RegToRename)) {
+              if (MOP.isReg() && !MOP.isDebug() && MOP.getReg() &&
+                  TRI->regsOverlap(MOP.getReg(), RegToRename)) {
                 assert(MOP.isImplicit() ||
                        (MOP.isRenamable() && !MOP.isEarlyClobber()) &&
                            "Need renamable operands");
@@ -913,7 +914,7 @@
              std::next(I), std::next(Paired)))
       assert(all_of(MI.operands(),
                     [this, &RenameReg](const MachineOperand &MOP) {
-                      return !MOP.isReg() || MOP.isDebug() ||
+                      return !MOP.isReg() || MOP.isDebug() || !MOP.getReg() ||
                              !TRI->regsOverlap(MOP.getReg(), *RenameReg);
                     }) &&
              "Rename register used between paired instruction, trashing the "
@@ -1348,7 +1349,8 @@
   if (!getLdStRegOp(FirstMI).isKill() &&
       !any_of(FirstMI.operands(),
               [TRI, RegToRename](const MachineOperand &MOP) {
-                return MOP.isReg() && MOP.isImplicit() && MOP.isKill() &&
+                return MOP.isReg() && !MOP.isDebug() && MOP.getReg() &&
+                       MOP.isImplicit() && MOP.isKill() &&
                        TRI->regsOverlap(RegToRename, MOP.getReg());
               })) {
     LLVM_DEBUG(dbgs() << "  Operand not killed at " << FirstMI << "\n");
@@ -1384,7 +1386,7 @@
     // For defs, check if we can rename the first def of RegToRename.
     if (FoundDef) {
       for (auto &MOP : MI.operands()) {
-        if (!MOP.isReg() || !MOP.isDef() ||
+        if (!MOP.isReg() || !MOP.isDef() || MOP.isDebug() || !MOP.getReg() ||
             !TRI->regsOverlap(MOP.getReg(), RegToRename))
           continue;
         if (!canRenameMOP(MOP)) {
@@ -1397,7 +1399,8 @@
       return true;
     } else {
       for (auto &MOP : MI.operands()) {
-        if (!MOP.isReg() || !TRI->regsOverlap(MOP.getReg(), RegToRename))
+        if (!MOP.isReg() || MOP.isDebug() || !MOP.getReg() ||
+            !TRI->regsOverlap(MOP.getReg(), RegToRename))
           continue;
 
         if (!canRenameMOP(MOP)) {