commit 26cb53b2605e2626f0c0f4d64affb82625915612
author Matt Arsenault <Matthew.Arsenault@amd.com> Thu Aug 01 03:33:15 2019 +0000
committer Matt Arsenault <Matthew.Arsenault@amd.com> Thu Aug 01 03:33:15 2019 +0000
tree 91ee9bc2846305ceb6d1c16d52fe7c1a0cd9b913
parent 4e3e54ab72ad6a92dfe1b4d8cd525a38df27b2d9

AMDGPU/GlobalISel: Handle G_ATOMICRMW_FADD

llvm-svn: 367509

llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index baceab3..aaa5132 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -593,6 +593,9 @@
     Atomics.legalFor({{S32, FlatPtr}, {S64, FlatPtr}});
   }
 
+  getActionDefinitionsBuilder(G_ATOMICRMW_FADD)
+    .legalFor({{S32, LocalPtr}});
+
   // TODO: Pointer types, any 32-bit or 64-bit vector
   getActionDefinitionsBuilder(G_SELECT)
     .legalForCartesianProduct({S32, S64, S16, V2S32, V2S16, V4S16,