[PowerPC] Infrastructure work. Implement getting the opcode for a spill in one place.
A new function getOpcodeForSpill should now be the only place to get
the opcode for a given spilled register.
Differential Revision: https://reviews.llvm.org/D43086
llvm-svn: 328556
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.h b/llvm/lib/Target/PowerPC/PPCInstrInfo.h
index 3eba41f..ba82f56 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.h
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.h
@@ -68,7 +68,9 @@
/// The VSX instruction that uses VSX register (vs0-vs63), instead of VMX
/// register (v0-v31).
- UseVSXReg = 0x1 << NewDef_Shift
+ UseVSXReg = 0x1 << NewDef_Shift,
+ /// This instruction is an X-Form memory operation.
+ XFormMemOp = 0x1 << (NewDef_Shift+1)
};
} // end namespace PPCII
@@ -114,20 +116,19 @@
PPCSubtarget &Subtarget;
const PPCRegisterInfo RI;
- bool StoreRegToStackSlot(MachineFunction &MF,
- unsigned SrcReg, bool isKill, int FrameIdx,
- const TargetRegisterClass *RC,
- SmallVectorImpl<MachineInstr*> &NewMIs,
- bool &NonRI, bool &SpillsVRS) const;
- bool LoadRegFromStackSlot(MachineFunction &MF, const DebugLoc &DL,
+ void StoreRegToStackSlot(MachineFunction &MF, unsigned SrcReg, bool isKill,
+ int FrameIdx, const TargetRegisterClass *RC,
+ SmallVectorImpl<MachineInstr *> &NewMIs) const;
+ void LoadRegFromStackSlot(MachineFunction &MF, const DebugLoc &DL,
unsigned DestReg, int FrameIdx,
const TargetRegisterClass *RC,
- SmallVectorImpl<MachineInstr *> &NewMIs,
- bool &NonRI, bool &SpillsVRS) const;
+ SmallVectorImpl<MachineInstr *> &NewMIs) const;
bool transformToImmForm(MachineInstr &MI, const ImmInstrInfo &III,
unsigned ConstantOpNo, int64_t Imm) const;
MachineInstr *getConstantDefMI(MachineInstr &MI, unsigned &ConstOp,
bool &SeenIntermediateUse) const;
+ const unsigned *getStoreOpcodesForSpillArray() const;
+ const unsigned *getLoadOpcodesForSpillArray() const;
virtual void anchor();
protected:
@@ -154,6 +155,10 @@
///
const PPCRegisterInfo &getRegisterInfo() const { return RI; }
+ bool isXFormMemOp(unsigned Opcode) const {
+ return get(Opcode).TSFlags & PPCII::XFormMemOp;
+ }
+
ScheduleHazardRecognizer *
CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
const ScheduleDAG *DAG) const override;
@@ -251,6 +256,12 @@
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const override;
+ unsigned getStoreOpcodeForSpill(unsigned Reg,
+ const TargetRegisterClass *RC = nullptr) const;
+
+ unsigned getLoadOpcodeForSpill(unsigned Reg,
+ const TargetRegisterClass *RC = nullptr) const;
+
bool
reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;