[Hexagon] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC).
llvm-svn: 289907
diff --git a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
index 2281148..a3f6273 100644
--- a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
@@ -17,26 +17,51 @@
#include "HexagonRegisterInfo.h"
#include "HexagonSubtarget.h"
#include "HexagonTargetMachine.h"
+#include "MCTargetDesc/HexagonBaseInfo.h"
#include "llvm/ADT/BitVector.h"
+#include "llvm/ADT/DenseMap.h"
+#include "llvm/ADT/None.h"
+#include "llvm/ADT/Optional.h"
#include "llvm/ADT/PostOrderIterator.h"
+#include "llvm/ADT/SetVector.h"
+#include "llvm/ADT/SmallSet.h"
+#include "llvm/ADT/SmallVector.h"
#include "llvm/CodeGen/LivePhysRegs.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineDominators.h"
+#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
-#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
+#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachinePostDominators.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegisterScavenging.h"
+#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/Function.h"
-#include "llvm/IR/Type.h"
+#include "llvm/MC/MCDwarf.h"
+#include "llvm/MC/MCRegisterInfo.h"
+#include "llvm/Pass.h"
+#include "llvm/Support/CodeGen.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
+#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetOptions.h"
+#include "llvm/Target/TargetRegisterInfo.h"
+#include <algorithm>
+#include <cassert>
+#include <cstdint>
+#include <iterator>
+#include <limits>
+#include <map>
+#include <new>
+#include <utility>
+#include <vector>
// Hexagon stack frame layout as defined by the ABI:
//
@@ -120,7 +145,6 @@
// alignment)
// A - required alignment
-
using namespace llvm;
static cl::opt<bool> DisableDeallocRet("disable-hexagon-dealloc-ret",
@@ -146,9 +170,9 @@
cl::init(true), cl::Hidden, cl::ZeroOrMore,
cl::desc("Enable stack frame shrink wrapping"));
-static cl::opt<unsigned> ShrinkLimit("shrink-frame-limit", cl::init(UINT_MAX),
- cl::Hidden, cl::ZeroOrMore, cl::desc("Max count of stack frame "
- "shrink-wraps"));
+static cl::opt<unsigned> ShrinkLimit("shrink-frame-limit",
+ cl::init(std::numeric_limits<unsigned>::max()), cl::Hidden, cl::ZeroOrMore,
+ cl::desc("Max count of stack frame shrink-wraps"));
static cl::opt<bool> EnableSaveRestoreLong("enable-save-restore-long",
cl::Hidden, cl::desc("Enable long calls for save-restore stubs."),
@@ -162,25 +186,30 @@
#ifndef NDEBUG
static cl::opt<unsigned> SpillOptMax("spill-opt-max", cl::Hidden,
- cl::init(UINT_MAX));
+ cl::init(std::numeric_limits<unsigned>::max()));
static unsigned SpillOptCount = 0;
#endif
-
namespace llvm {
+
void initializeHexagonCallFrameInformationPass(PassRegistry&);
FunctionPass *createHexagonCallFrameInformation();
-}
+
+} // end namespace llvm
namespace {
+
class HexagonCallFrameInformation : public MachineFunctionPass {
public:
static char ID;
+
HexagonCallFrameInformation() : MachineFunctionPass(ID) {
PassRegistry &PR = *PassRegistry::getPassRegistry();
initializeHexagonCallFrameInformationPass(PR);
}
+
bool runOnMachineFunction(MachineFunction &MF) override;
+
MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set(
MachineFunctionProperties::Property::NoVRegs);
@@ -188,7 +217,8 @@
};
char HexagonCallFrameInformation::ID = 0;
-}
+
+} // end anonymous namespace
bool HexagonCallFrameInformation::runOnMachineFunction(MachineFunction &MF) {
auto &HFI = *MF.getSubtarget<HexagonSubtarget>().getFrameLowering();
@@ -208,12 +238,11 @@
return new HexagonCallFrameInformation();
}
-
-namespace {
- /// Map a register pair Reg to the subregister that has the greater "number",
- /// i.e. D3 (aka R7:6) will be mapped to R7, etc.
- unsigned getMax32BitSubRegister(unsigned Reg, const TargetRegisterInfo &TRI,
- bool hireg = true) {
+/// Map a register pair Reg to the subregister that has the greater "number",
+/// i.e. D3 (aka R7:6) will be mapped to R7, etc.
+static unsigned getMax32BitSubRegister(unsigned Reg,
+ const TargetRegisterInfo &TRI,
+ bool hireg = true) {
if (Reg < Hexagon::D0 || Reg > Hexagon::D15)
return Reg;
@@ -228,11 +257,11 @@
}
}
return RegNo;
- }
+}
- /// Returns the callee saved register with the largest id in the vector.
- unsigned getMaxCalleeSavedReg(const std::vector<CalleeSavedInfo> &CSI,
- const TargetRegisterInfo &TRI) {
+/// Returns the callee saved register with the largest id in the vector.
+static unsigned getMaxCalleeSavedReg(const std::vector<CalleeSavedInfo> &CSI,
+ const TargetRegisterInfo &TRI) {
static_assert(Hexagon::R1 > 0,
"Assume physical registers are encoded as positive integers");
if (CSI.empty())
@@ -245,12 +274,12 @@
Max = Reg;
}
return Max;
- }
+}
- /// Checks if the basic block contains any instruction that needs a stack
- /// frame to be already in place.
- bool needsStackFrame(const MachineBasicBlock &MBB, const BitVector &CSR,
- const HexagonRegisterInfo &HRI) {
+/// Checks if the basic block contains any instruction that needs a stack
+/// frame to be already in place.
+static bool needsStackFrame(const MachineBasicBlock &MBB, const BitVector &CSR,
+ const HexagonRegisterInfo &HRI) {
for (auto &I : MBB) {
const MachineInstr *MI = &I;
if (MI->isCall())
@@ -285,34 +314,34 @@
}
}
return false;
- }
+}
/// Returns true if MBB has a machine instructions that indicates a tail call
/// in the block.
- bool hasTailCall(const MachineBasicBlock &MBB) {
+static bool hasTailCall(const MachineBasicBlock &MBB) {
MachineBasicBlock::const_iterator I = MBB.getLastNonDebugInstr();
unsigned RetOpc = I->getOpcode();
return RetOpc == Hexagon::PS_tailcall_i || RetOpc == Hexagon::PS_tailcall_r;
- }
+}
- /// Returns true if MBB contains an instruction that returns.
- bool hasReturn(const MachineBasicBlock &MBB) {
+/// Returns true if MBB contains an instruction that returns.
+static bool hasReturn(const MachineBasicBlock &MBB) {
for (auto I = MBB.getFirstTerminator(), E = MBB.end(); I != E; ++I)
if (I->isReturn())
return true;
return false;
- }
+}
- /// Returns the "return" instruction from this block, or nullptr if there
- /// isn't any.
- MachineInstr *getReturn(MachineBasicBlock &MBB) {
+/// Returns the "return" instruction from this block, or nullptr if there
+/// isn't any.
+static MachineInstr *getReturn(MachineBasicBlock &MBB) {
for (auto &I : MBB)
if (I.isReturn())
return &I;
return nullptr;
- }
+}
- bool isRestoreCall(unsigned Opc) {
+static bool isRestoreCall(unsigned Opc) {
switch (Opc) {
case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC:
@@ -325,23 +354,21 @@
return true;
}
return false;
- }
-
- inline bool isOptNone(const MachineFunction &MF) {
- return MF.getFunction()->hasFnAttribute(Attribute::OptimizeNone) ||
- MF.getTarget().getOptLevel() == CodeGenOpt::None;
- }
-
- inline bool isOptSize(const MachineFunction &MF) {
- const Function &F = *MF.getFunction();
- return F.optForSize() && !F.optForMinSize();
- }
-
- inline bool isMinSize(const MachineFunction &MF) {
- return MF.getFunction()->optForMinSize();
- }
}
+static inline bool isOptNone(const MachineFunction &MF) {
+ return MF.getFunction()->hasFnAttribute(Attribute::OptimizeNone) ||
+ MF.getTarget().getOptLevel() == CodeGenOpt::None;
+}
+
+static inline bool isOptSize(const MachineFunction &MF) {
+ const Function &F = *MF.getFunction();
+ return F.optForSize() && !F.optForMinSize();
+}
+
+static inline bool isMinSize(const MachineFunction &MF) {
+ return MF.getFunction()->optForMinSize();
+}
/// Implements shrink-wrapping of the stack frame. By default, stack frame
/// is created in the function entry block, and is cleaned up in every block
@@ -447,7 +474,6 @@
EpilogB = PDomB;
}
-
/// Perform most of the PEI work here:
/// - saving/restoring of the callee-saved registers,
/// - stack frame creation and destruction.
@@ -503,7 +529,6 @@
}
}
-
void HexagonFrameLowering::insertPrologueInBlock(MachineBasicBlock &MBB,
bool PrologueStubs) const {
MachineFunction &MF = *MBB.getParent();
@@ -736,9 +761,8 @@
return ReachedExit;
}
-
-namespace {
- Optional<MachineBasicBlock::iterator> findCFILocation(MachineBasicBlock &B) {
+static Optional<MachineBasicBlock::iterator>
+findCFILocation(MachineBasicBlock &B) {
// The CFI instructions need to be inserted right after allocframe.
// An exception to this is a situation where allocframe is bundled
// with a call: then the CFI instructions need to be inserted before
@@ -766,10 +790,8 @@
return HasCall ? It : std::next(It);
}
return None;
- }
}
-
void HexagonFrameLowering::insertCFIInstructions(MachineFunction &MF) const {
for (auto &B : MF) {
auto At = findCFILocation(B);
@@ -778,7 +800,6 @@
}
}
-
void HexagonFrameLowering::insertCFIInstructionsAt(MachineBasicBlock &MBB,
MachineBasicBlock::iterator At) const {
MachineFunction &MF = *MBB.getParent();
@@ -892,7 +913,6 @@
}
}
-
bool HexagonFrameLowering::hasFP(const MachineFunction &MF) const {
auto &MFI = MF.getFrameInfo();
auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
@@ -930,7 +950,6 @@
return false;
}
-
enum SpillKind {
SK_ToMem,
SK_FromMem,
@@ -1005,10 +1024,9 @@
default:
llvm_unreachable("Unhandled maximum callee save register");
}
- return 0;
+ return nullptr;
}
-
int HexagonFrameLowering::getFrameIndexReference(const MachineFunction &MF,
int FI, unsigned &FrameReg) const {
auto &MFI = MF.getFrameInfo();
@@ -1092,7 +1110,6 @@
return RealOffset;
}
-
bool HexagonFrameLowering::insertCSRSpillsInBlock(MachineBasicBlock &MBB,
const CSIVect &CSI, const HexagonRegisterInfo &HRI,
bool &PrologueStubs) const {
@@ -1161,7 +1178,6 @@
return true;
}
-
bool HexagonFrameLowering::insertCSRRestoresInBlock(MachineBasicBlock &MBB,
const CSIVect &CSI, const HexagonRegisterInfo &HRI) const {
if (CSI.empty())
@@ -1237,7 +1253,6 @@
return MBB.erase(I);
}
-
void HexagonFrameLowering::processFunctionBeforeFrameFinalized(
MachineFunction &MF, RegScavenger *RS) const {
// If this function has uses aligned stack and also has variable sized stack
@@ -1301,7 +1316,6 @@
return true;
}
-
#ifndef NDEBUG
static void dump_registers(BitVector &Regs, const TargetRegisterInfo &TRI) {
dbgs() << '{';
@@ -1313,7 +1327,6 @@
}
#endif
-
bool HexagonFrameLowering::assignCalleeSavedSpillSlots(MachineFunction &MF,
const TargetRegisterInfo *TRI, std::vector<CalleeSavedInfo> &CSI) const {
DEBUG(dbgs() << __func__ << " on "
@@ -1534,7 +1547,6 @@
return true;
}
-
bool HexagonFrameLowering::expandStoreVecPred(MachineBasicBlock &B,
MachineBasicBlock::iterator It, MachineRegisterInfo &MRI,
const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const {
@@ -1809,7 +1821,6 @@
return true;
}
-
bool HexagonFrameLowering::expandSpillMacros(MachineFunction &MF,
SmallVectorImpl<unsigned> &NewRegs) const {
auto &HST = MF.getSubtarget<HexagonSubtarget>();
@@ -1864,7 +1875,6 @@
return Changed;
}
-
void HexagonFrameLowering::determineCalleeSaves(MachineFunction &MF,
BitVector &SavedRegs,
RegScavenger *RS) const {
@@ -1913,7 +1923,6 @@
TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
}
-
unsigned HexagonFrameLowering::findPhysReg(MachineFunction &MF,
HexagonBlockRanges::IndexRange &FIR,
HexagonBlockRanges::InstrIndexMap &IndexMap,
@@ -1962,10 +1971,10 @@
struct SlotInfo {
BlockRangeMap Map;
- unsigned Size;
- const TargetRegisterClass *RC;
+ unsigned Size = 0;
+ const TargetRegisterClass *RC = nullptr;
- SlotInfo() : Map(), Size(0), RC(nullptr) {}
+ SlotInfo() = default;
};
BlockIndexMap BlockIndexes;
@@ -2324,7 +2333,6 @@
}
}
-
bool HexagonFrameLowering::needsAligna(const MachineFunction &MF) const {
const MachineFrameInfo &MFI = MF.getFrameInfo();
if (!MFI.hasVarSizedObjects())
@@ -2335,7 +2343,6 @@
return true;
}
-
const MachineInstr *HexagonFrameLowering::getAlignaInstr(
const MachineFunction &MF) const {
for (auto &B : MF)
@@ -2345,7 +2352,6 @@
return nullptr;
}
-
/// Adds all callee-saved registers as implicit uses or defs to the
/// instruction.
void HexagonFrameLowering::addCalleeSaveRegistersAsImpOperand(MachineInstr *MI,
@@ -2355,7 +2361,6 @@
MI->addOperand(MachineOperand::CreateReg(R.getReg(), IsDef, true, IsKill));
}
-
/// Determine whether the callee-saved register saves and restores should
/// be generated via inline code. If this function returns "true", inline
/// code will be generated. If this function returns "false", additional
@@ -2390,7 +2395,6 @@
return false;
}
-
bool HexagonFrameLowering::useSpillFunction(MachineFunction &MF,
const CSIVect &CSI) const {
if (shouldInlineCSR(MF, CSI))
@@ -2404,7 +2408,6 @@
return Threshold < NumCSI;
}
-
bool HexagonFrameLowering::useRestoreFunction(MachineFunction &MF,
const CSIVect &CSI) const {
if (shouldInlineCSR(MF, CSI))
@@ -2426,7 +2429,6 @@
return Threshold < NumCSI;
}
-
bool HexagonFrameLowering::mayOverflowFrameOffset(MachineFunction &MF) const {
unsigned StackSize = MF.getFrameInfo().estimateStackSize(MF);
auto &HST = MF.getSubtarget<HexagonSubtarget>();
@@ -2437,4 +2439,3 @@
return StackSize > 256;
return false;
}
-