[Hexagon] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC).
llvm-svn: 289907
diff --git a/llvm/lib/Target/Hexagon/HexagonGenMux.cpp b/llvm/lib/Target/Hexagon/HexagonGenMux.cpp
index c780db8..a718df9 100644
--- a/llvm/lib/Target/Hexagon/HexagonGenMux.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonGenMux.cpp
@@ -22,33 +22,57 @@
#define DEBUG_TYPE "hexmux"
-#include "llvm/CodeGen/Passes.h"
+#include "HexagonInstrInfo.h"
+#include "HexagonRegisterInfo.h"
+#include "HexagonSubtarget.h"
+#include "llvm/ADT/BitVector.h"
+#include "llvm/ADT/SmallVector.h"
+#include "llvm/ADT/StringRef.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
+#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
-#include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "HexagonTargetMachine.h"
+#include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/IR/DebugLoc.h"
+#include "llvm/MC/MCInstrDesc.h"
+#include "llvm/MC/MCRegisterInfo.h"
+#include "llvm/Pass.h"
+#include "llvm/Support/MathExtras.h"
+#include <algorithm>
+#include <limits>
+#include <iterator>
+#include <utility>
using namespace llvm;
namespace llvm {
+
FunctionPass *createHexagonGenMux();
void initializeHexagonGenMuxPass(PassRegistry& Registry);
-}
+
+} // end namespace llvm
namespace {
+
class HexagonGenMux : public MachineFunctionPass {
public:
static char ID;
- HexagonGenMux() : MachineFunctionPass(ID), HII(0), HRI(0) {
+
+ HexagonGenMux() : MachineFunctionPass(ID), HII(nullptr), HRI(nullptr) {
initializeHexagonGenMuxPass(*PassRegistry::getPassRegistry());
}
+
StringRef getPassName() const override {
return "Hexagon generate mux instructions";
}
+
void getAnalysisUsage(AnalysisUsage &AU) const override {
MachineFunctionPass::getAnalysisUsage(AU);
}
+
bool runOnMachineFunction(MachineFunction &MF) override;
+
MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set(
MachineFunctionProperties::Property::NoVRegs);
@@ -59,26 +83,33 @@
const HexagonRegisterInfo *HRI;
struct CondsetInfo {
- unsigned PredR;
- unsigned TrueX, FalseX;
- CondsetInfo() : PredR(0), TrueX(UINT_MAX), FalseX(UINT_MAX) {}
+ unsigned PredR = 0;
+ unsigned TrueX = std::numeric_limits<unsigned>::max();
+ unsigned FalseX = std::numeric_limits<unsigned>::max();
+
+ CondsetInfo() = default;
};
+
struct DefUseInfo {
BitVector Defs, Uses;
- DefUseInfo() : Defs(), Uses() {}
+
+ DefUseInfo() = default;
DefUseInfo(const BitVector &D, const BitVector &U) : Defs(D), Uses(U) {}
};
+
struct MuxInfo {
MachineBasicBlock::iterator At;
unsigned DefR, PredR;
MachineOperand *SrcT, *SrcF;
MachineInstr *Def1, *Def2;
+
MuxInfo(MachineBasicBlock::iterator It, unsigned DR, unsigned PR,
MachineOperand *TOp, MachineOperand *FOp, MachineInstr &D1,
MachineInstr &D2)
: At(It), DefR(DR), PredR(PR), SrcT(TOp), SrcF(FOp), Def1(&D1),
Def2(&D2) {}
};
+
typedef DenseMap<MachineInstr*,unsigned> InstrIndexMap;
typedef DenseMap<unsigned,DefUseInfo> DefUseInfoMap;
typedef SmallVector<MuxInfo,4> MuxInfoList;
@@ -86,6 +117,7 @@
bool isRegPair(unsigned Reg) const {
return Hexagon::DoubleRegsRegClass.contains(Reg);
}
+
void getSubRegs(unsigned Reg, BitVector &SRs) const;
void expandReg(unsigned Reg, BitVector &Set) const;
void getDefsUses(const MachineInstr *MI, BitVector &Defs,
@@ -99,18 +131,17 @@
};
char HexagonGenMux::ID = 0;
-}
+
+} // end anonymous namespace
INITIALIZE_PASS(HexagonGenMux, "hexagon-mux",
"Hexagon generate mux instructions", false, false)
-
void HexagonGenMux::getSubRegs(unsigned Reg, BitVector &SRs) const {
for (MCSubRegIterator I(Reg, HRI); I.isValid(); ++I)
SRs[*I] = true;
}
-
void HexagonGenMux::expandReg(unsigned Reg, BitVector &Set) const {
if (isRegPair(Reg))
getSubRegs(Reg, Set);
@@ -118,7 +149,6 @@
Set[Reg] = true;
}
-
void HexagonGenMux::getDefsUses(const MachineInstr *MI, BitVector &Defs,
BitVector &Uses) const {
// First, get the implicit defs and uses for this instruction.
@@ -141,7 +171,6 @@
}
}
-
void HexagonGenMux::buildMaps(MachineBasicBlock &B, InstrIndexMap &I2X,
DefUseInfoMap &DUM) {
unsigned Index = 0;
@@ -159,7 +188,6 @@
}
}
-
bool HexagonGenMux::isCondTransfer(unsigned Opc) const {
switch (Opc) {
case Hexagon::A2_tfrt:
@@ -171,7 +199,6 @@
return false;
}
-
unsigned HexagonGenMux::getMuxOpcode(const MachineOperand &Src1,
const MachineOperand &Src2) const {
bool IsReg1 = Src1.isReg(), IsReg2 = Src2.isReg();
@@ -188,7 +215,6 @@
return 0;
}
-
bool HexagonGenMux::genMuxInBlock(MachineBasicBlock &B) {
bool Changed = false;
InstrIndexMap I2X;
@@ -231,7 +257,8 @@
CI.TrueX = Idx;
else
CI.FalseX = Idx;
- if (CI.TrueX == UINT_MAX || CI.FalseX == UINT_MAX)
+ if (CI.TrueX == std::numeric_limits<unsigned>::max() ||
+ CI.FalseX == std::numeric_limits<unsigned>::max())
continue;
// There is now a complete definition of DR, i.e. we have the predicate