commit 26fa89e0a7791bd16ad33ef6a4836dacbff6b1ab
author Andrew Lenharth <andrewl@lenharth.org> Mon Jul 04 20:07:21 2005 +0000
committer Andrew Lenharth <andrewl@lenharth.org> Mon Jul 04 20:07:21 2005 +0000
tree 68ba023007d56f949f3b928240d8e459344113de
parent da852d51dff51f170dbd0088b2500a40126d7b57

check the correct VT

llvm-svn: 22332

llvm/lib/Target/Alpha/AlphaISelPattern.cpp

diff --git a/llvm/lib/Target/Alpha/AlphaISelPattern.cpp b/llvm/lib/Target/Alpha/AlphaISelPattern.cpp
index ed285a3..bef5293 100644
--- a/llvm/lib/Target/Alpha/AlphaISelPattern.cpp
+++ b/llvm/lib/Target/Alpha/AlphaISelPattern.cpp
@@ -1642,7 +1642,7 @@
       Select(Chain);
       unsigned r = dyn_cast<RegSDNode>(Node)->getReg();
       //std::cerr << "CopyFromReg " << Result << " = " << r << "\n";
-      if (isFP)
+      if (MVT::isFloatingPoint(N.getValue(0).getValueType()))
         BuildMI(BB, Alpha::CPYS, 2, Result).addReg(r).addReg(r);
       else
         BuildMI(BB, Alpha::BIS, 2, Result).addReg(r).addReg(r);