ARM: implement support for the UDF mnemonic
The UDF instruction is a reserved undefined instruction space. The assembler
mnemonic was introduced with ARM ARM rev C.a. The instruction is not predicated
and the immediate constant is ignored by the CPU. Add support for the three
encodings for this instruction.
The changes to the invalid instruction test is due to the fact that the invalid
instructions actually overlap with the undefined instruction. Introduction of
the new instruction results in a partial decode as an undefined sequence. Drop
the tests as they are invalid instruction patterns anyways.
llvm-svn: 208751
diff --git a/llvm/test/MC/ARM/udf-arm-diagnostics.s b/llvm/test/MC/ARM/udf-arm-diagnostics.s
new file mode 100644
index 0000000..9ec9bf2
--- /dev/null
+++ b/llvm/test/MC/ARM/udf-arm-diagnostics.s
@@ -0,0 +1,19 @@
+@ RUN: not llvm-mc -triple arm-eabi %s 2>&1 | FileCheck %s
+
+ .syntax unified
+ .text
+ .arm
+
+undefined:
+ udfpl
+
+@ CHECK: error: instruction 'udf' is not predicable, but condition code specified
+@ CHECK: udfpl
+@ CHECK: ^
+
+ udf #65536
+
+@ CHECK: error: invalid operand for instruction
+@ CHECK: udf #65536
+@ CHECK: ^
+
diff --git a/llvm/test/MC/ARM/udf-arm.s b/llvm/test/MC/ARM/udf-arm.s
new file mode 100644
index 0000000..a9d19ca
--- /dev/null
+++ b/llvm/test/MC/ARM/udf-arm.s
@@ -0,0 +1,11 @@
+@ RUN: llvm-mc -triple arm-eabi -show-encoding %s | FileCheck %s
+
+ .syntax unified
+ .text
+ .arm
+
+undefined:
+ udf #0
+
+@ CHECK: udf #0 @ encoding: [0xf0,0x00,0xf0,0xe7]
+
diff --git a/llvm/test/MC/ARM/udf-thumb-2-diagnostics.s b/llvm/test/MC/ARM/udf-thumb-2-diagnostics.s
new file mode 100644
index 0000000..f837560
--- /dev/null
+++ b/llvm/test/MC/ARM/udf-thumb-2-diagnostics.s
@@ -0,0 +1,25 @@
+@ RUN: not llvm-mc -triple thumbv7-eabi -mattr +thumb2 %s 2>&1 | FileCheck %s
+
+ .syntax unified
+ .text
+ .thumb
+
+undefined:
+ udfpl
+
+@ CHECK: error: instruction 'udf' is not predicable, but condition code specified
+@ CHECK: udfpl
+@ CHECK: ^
+
+ udf #256
+
+@ CHECK: error: instruction requires: arm-mode
+@ CHECK: udf #256
+@ CHECK: ^
+
+ udf.w #65536
+
+@ CHECK: error: invalid operand for instruction
+@ CHECK: udf.w #65536
+@ CHECK: ^
+
diff --git a/llvm/test/MC/ARM/udf-thumb-2.s b/llvm/test/MC/ARM/udf-thumb-2.s
new file mode 100644
index 0000000..beb6549
--- /dev/null
+++ b/llvm/test/MC/ARM/udf-thumb-2.s
@@ -0,0 +1,13 @@
+@ RUN: llvm-mc -triple thumbv7-eabi -mattr +thumb2 -show-encoding %s | FileCheck %s
+
+ .syntax unified
+ .text
+ .thumb
+
+undefined:
+ udf #0
+ udf.w #0
+
+@ CHECK: udf #0 @ encoding: [0x00,0xde]
+@ CHECK: udf.w #0 @ encoding: [0xf0,0xf7,0x00,0xa0]
+
diff --git a/llvm/test/MC/ARM/udf-thumb-diagnostics.s b/llvm/test/MC/ARM/udf-thumb-diagnostics.s
new file mode 100644
index 0000000..51388d0
--- /dev/null
+++ b/llvm/test/MC/ARM/udf-thumb-diagnostics.s
@@ -0,0 +1,19 @@
+@ RUN: not llvm-mc -triple thumbv6m-eabi %s 2>&1 | FileCheck %s
+
+ .syntax unified
+ .text
+ .thumb
+
+undefined:
+ udfpl
+
+@ CHECK: error: conditional execution not supported in Thumb1
+@ CHECK: udfpl
+@ CHECK: ^
+
+ udf #256
+
+@ CHECK: error: instruction requires: arm-mode
+@ CHECK: udf #256
+@ CHECK: ^
+
diff --git a/llvm/test/MC/ARM/udf-thumb.s b/llvm/test/MC/ARM/udf-thumb.s
new file mode 100644
index 0000000..10b3aff
--- /dev/null
+++ b/llvm/test/MC/ARM/udf-thumb.s
@@ -0,0 +1,11 @@
+@ RUN: llvm-mc -triple thumbv6m-eabi -show-encoding %s | FileCheck %s
+
+ .syntax unified
+ .text
+ .thumb
+
+undefined:
+ udf #0
+
+@ CHECK: udf #0 @ encoding: [0x00,0xde]
+
diff --git a/llvm/test/MC/Disassembler/ARM/invalid-thumbv7.txt b/llvm/test/MC/Disassembler/ARM/invalid-thumbv7.txt
index 2c84b8a..5257633 100644
--- a/llvm/test/MC/Disassembler/ARM/invalid-thumbv7.txt
+++ b/llvm/test/MC/Disassembler/ARM/invalid-thumbv7.txt
@@ -21,17 +21,6 @@
# CHECK: warning: invalid instruction encoding
# CHECK-NEXT: [0xaf 0xf7 0x44 0x8b]
-# Opcode=2249 Name=tBcc Format=ARM_FORMAT_THUMBFRM(25)
-# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-# -------------------------------------------------------------------------------------------------
-# | 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 1: 1: 0: 1| 1: 1: 1: 0| 0: 1: 1: 0| 1: 1: 1: 1|
-# -------------------------------------------------------------------------------------------------
-#
-# if cond = '1110' then UNDEFINED
-[0x6f 0xde]
-# CHECK: invalid instruction encoding
-# CHECK-NEXT: [0x6f 0xde]
-
#------------------------------------------------------------------------------
# Undefined encoding for it
#------------------------------------------------------------------------------
@@ -249,34 +238,6 @@
# CHECK-NEXT: [0xe4 0xe9 0x02 0x46]
#------------------------------------------------------------------------------
-# Undefined encodings for NEON/VFP instructions with invalid predicate bits
-#------------------------------------------------------------------------------
-
-# VABS
-[0x40 0xde 0x00 0x0a]
-# CHECK: invalid instruction encoding
-# CHECK-NEXT: [0x40 0xde 0x00 0x0a]
-
-
-# VMLA
-[0xf0 0xde 0xe0 0x0b]
-# CHECK: invalid instruction encoding
-# CHECK-NEXT: [0xf0 0xde 0xe0 0x0b]
-
-# VMOV/VDUP between scalar and core registers with invalid predicate bits (pred != 0b1110)
-
-# VMOV
-[0x00 0xde 0x10 0x0b]
-# CHECK: invalid instruction encoding
-# CHECK-NEXT: [0x00 0xde 0x10 0x0b]
-
-# VDUP
-[0xff 0xde 0xf0 0xfb]
-# CHECK: invalid instruction encoding
-# CHECK-NEXT: [0xff 0xde 0xf0 0xfb]
-
-
-#------------------------------------------------------------------------------
# Undefined encodings for NEON vld instructions
#------------------------------------------------------------------------------