* Changed Bcc instructions to behave like BPcc instructions
* BPA and BPN do not take a %cc register as a parameter
* SLL/SRL/SRA{r,i}5 are there for a reason - they are ONLY 32-bit instructions
* Likewise, SLL/SRL/SRAX{r,i}6 are only 64-bit
* Added WRCCR{r,i} opcodes
llvm-svn: 6655
diff --git a/llvm/lib/Target/Sparc/PrologEpilogCodeInserter.cpp b/llvm/lib/Target/Sparc/PrologEpilogCodeInserter.cpp
index 5aa74f3..babb470 100644
--- a/llvm/lib/Target/Sparc/PrologEpilogCodeInserter.cpp
+++ b/llvm/lib/Target/Sparc/PrologEpilogCodeInserter.cpp
@@ -86,7 +86,7 @@
M->setOperandLo32(1);
mvec.push_back(M);
- M = BuildMI(V9::SRAi6, 3).addMReg(uregNum).addZImm(0)
+ M = BuildMI(V9::SRAi5, 3).addMReg(uregNum).addZImm(0)
.addMReg(uregNum, MOTy::Def);
mvec.push_back(M);