* Changed Bcc instructions to behave like BPcc instructions
* BPA and BPN do not take a %cc register as a parameter
* SLL/SRL/SRA{r,i}5 are there for a reason - they are ONLY 32-bit instructions
* Likewise, SLL/SRL/SRAX{r,i}6 are only 64-bit
* Added WRCCR{r,i} opcodes
llvm-svn: 6655
diff --git a/llvm/lib/Target/Sparc/SparcInstrSelectionSupport.h b/llvm/lib/Target/Sparc/SparcInstrSelectionSupport.h
index 7f9bdc8..1be1de1 100644
--- a/llvm/lib/Target/Sparc/SparcInstrSelectionSupport.h
+++ b/llvm/lib/Target/Sparc/SparcInstrSelectionSupport.h
@@ -110,9 +110,9 @@
case V9::XNORccr: return V9::XNORcci;
/* shift */
- case V9::SLLr6: return V9::SLLi6;
- case V9::SRLr6: return V9::SRLi6;
- case V9::SRAr6: return V9::SRAi6;
+ case V9::SLLr5: return V9::SLLi5;
+ case V9::SRLr5: return V9::SRLi5;
+ case V9::SRAr5: return V9::SRAi5;
case V9::SLLXr6: return V9::SLLXi6;
case V9::SRLXr6: return V9::SRLXi6;
case V9::SRAXr6: return V9::SRAXi6;